New line of Intel Xeon 5500 (Nehalem) processors
Earlier this year, Intel introduced a new line of Xeon 5500 processors based on the Nehalem core. I met her at a seminar held by Trinity Solutions in Moscow on April 14.
What is interesting about the new series, except for the increase in productivity and reduction of energy consumption (without which nowhere)?
')
First of all, notice that all the processors in this line are multi-core (and only one of them is 2-core). In conjunction with Hyper Threading technology, this gives up to 16 logical cores (as we know, some systems, for example, Win2k3, perceive single-core processors with HT as dual core). In addition, Intel Turbo Boost technology allows you to dynamically change the frequency of each physical core separately to achieve the optimum performance / power consumption ratio depending on the load.
But, if HT and ITB are not the newest or even the most interesting developments, then QPI (QuickPath Interconnect) and IMC (Integrated Memory Controller) are new developments. If the second one is more or less clear from the name (I only added something, then the controller can work with DDR III in three-channel mode), then the first one is (IMHO) the most interesting innovation.
What is QPI? QPI is a high-speed bus for exchanging data between processors (i.e. a processor-to-processor connection) and a chipset (a processor-to-chipset connection). The data transfer rate is 25.6 GB / s. At the same time, the bus can automatically fix connection errors (as one of the seminar participants noted, it can work, not work and pretend that it works). The main advantage of such a system is that if in the past there was an inevitable conflict between hardware and BSOD in the OS (or kernel panic in another OS :) if there were any problems between the processors in the multiprocessor system, then if there are critical QPI errors make attempts to fix them on the fly (a sign of this will be a decrease in performance). The main task of the “processor-processor” connection is the exchange of data from the main memory (the memory controller integrated into the processor dictates the need to divide the memory into groups according to the number of processors in the system) between the processors. Processor-chipset connections allow processors to exchange data with PCI devices, disk systems, and so on.
Well, to top it off a few links:
PS This is the first attempt to write habratopik. So I will be glad to any criticism.
What is interesting about the new series, except for the increase in productivity and reduction of energy consumption (without which nowhere)?
')
First of all, notice that all the processors in this line are multi-core (and only one of them is 2-core). In conjunction with Hyper Threading technology, this gives up to 16 logical cores (as we know, some systems, for example, Win2k3, perceive single-core processors with HT as dual core). In addition, Intel Turbo Boost technology allows you to dynamically change the frequency of each physical core separately to achieve the optimum performance / power consumption ratio depending on the load.
But, if HT and ITB are not the newest or even the most interesting developments, then QPI (QuickPath Interconnect) and IMC (Integrated Memory Controller) are new developments. If the second one is more or less clear from the name (I only added something, then the controller can work with DDR III in three-channel mode), then the first one is (IMHO) the most interesting innovation.
What is QPI? QPI is a high-speed bus for exchanging data between processors (i.e. a processor-to-processor connection) and a chipset (a processor-to-chipset connection). The data transfer rate is 25.6 GB / s. At the same time, the bus can automatically fix connection errors (as one of the seminar participants noted, it can work, not work and pretend that it works). The main advantage of such a system is that if in the past there was an inevitable conflict between hardware and BSOD in the OS (or kernel panic in another OS :) if there were any problems between the processors in the multiprocessor system, then if there are critical QPI errors make attempts to fix them on the fly (a sign of this will be a decrease in performance). The main task of the “processor-processor” connection is the exchange of data from the main memory (the memory controller integrated into the processor dictates the need to divide the memory into groups according to the number of processors in the system) between the processors. Processor-chipset connections allow processors to exchange data with PCI devices, disk systems, and so on.
Well, to top it off a few links:
- Intel Xeon 5000 thread processor page
You can find a funny demo and product brief on it (eng.); - Event Page of Trinity Solutions Company
Below are links to seminar materials.
PS This is the first attempt to write habratopik. So I will be glad to any criticism.
Source: https://habr.com/ru/post/60408/
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