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Training camp on circuit design for tanks and bookmarks to processors

In April there was a rosnanovsky seminar on modern circuitry for school students of the Olympiad type . After him, a group of organizers gathered in the lobby and puzzled for a long time how to make the subject more interesting and useful. To enter Verilog and FPGA for example in the format of the Olympiad of STI. It was decided to abandon the mathematically interesting, but somewhat abstract for the student tasks such as the protocols of coherence caches in multiprocessor systems. Also, the idea of ​​an automatic greenhouse with sensors did not arouse much enthusiasm, since it was implemented a hundred times by the Arduino and STM32, and FPGAs do not add anything interesting to the greenhouses.

And suddenly - Eureka! And if we hold competitions on graphic games made on pure circuitry, without programming, as our ancestors did in the times of Brezhnev and Carter, like pin-pong games did. And to carry out not on ancient K561 microcircuits, but on modern Xilinx and Altera (in other words, Intel FPGA) and using the same design technologies at the register transfer level used by designers at Apple, Intel and SpaceX.

In short, we will deal with this in July 8-26 at the summer school in Zelenograd . Part of the school, which will be dealt with in terms of this post, is devoted to the basics of digital circuitry, the first steps in the architecture and microarchitecture of processors, and also (even more likely mostly) hardware-based computer graphics.
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I will try to bring my daughter student, Elizabeth, to Zelenograd as an assistant if she receives her passport and Russian visa on time. Elizabeth, being Russian-Ukrainian-Japanese, speaks only English. Here in Zelenograd and learn the basics of Russian. And at the same time teach the correct English pronunciation of instructors who are ready to help at the school (not necessarily from MIET, you can from MIPT, MSU, MEPI):



Today I made one of the examples for school - the game of tanchiki. Most of the code I took from the example in the book Designing Video Game Hardware in Verilog by Steven Hugg, December 15, 2018 . Stephen Hugg showed the code on some beautiful, but non-industrial simulator. I think that learning on such a simulator is like sniffing flowers in a gas mask, so I synthesized the code and poured the resulting configuration into real iron — a cheap Chinese ZEOWAA board . To do this, I had to rewrite the VGA sweep generation, make the code more synthesizable, and remove some methodological irregularities in using clock signals. Laid out the result on github .

Here is how it looks in the simulator Stephen Hagg:



Here is how it looks in my first approximation, after mechanically combining the wrapper for the board, the sweep generator and the Stephen code, as well as fixing any small things that do not work in Intel FPGA Quartus Lite Edition, synthesis and fill:



But the camp will not only be about games with VGA sweep generation, ROM, sprites and so on. We also cross it with processors. To compare the implementation of games on hardware finite automata with a hardware-software implementation. To do this, we use the schoolMIPS training processor core, which is described in the posts of Stanislav Zhelio on Habré and the schoolMIPS wiki on GitHub .

You can even use the schoolMIPS training kernel to demonstrate how to design bookmarks to processors. We will not argue whether there are bookmarks in the processor of a computer on your desk, in your phone or car. We will show how to design them. Example of a bookmark: a hardware state machine monitors the contents of the architectural registers during program execution, and when the text “Cloudless sky over all Spain” appears in them, switches the processor to privileged mode. Text can come from a user program, for example, an email client.

Is it possible to detect such a tab with a software antivirus? Not. Software does not see this at all until it happens. Is it possible to detect by examining the chip under an electron microscope? Also not, in the industrial processor billions of transistors, even in the Arduin - hundreds of thousands. Even if you have the source of the processor, you can hide a lot in the tens or hundreds of thousands or millions of lines on the chain, especially if different parts of the processor carry out parts of a cleverly thought out plan.

You can even organize a contest when one team creates a bookmark, and the other finds it.



Any schoolchild who has completed three modules of the theoretical online course from RUSNANO with a career-oriented overview of modern chip design methods can participate in the summer school in Zelenograd (all this for free and even with the issuance of prizes):

  1. From transistor to microchip
  2. The logical side of digital circuitry
  3. The physical side of digital circuitry


The preliminary program of the course - discussion on it is welcome:

Week 1. Basics of digital logic.

Day 1. Chips of a small degree of integration, exercises with combinatorial logic.
Day 2. Chips of a small degree of integration, exercises with sequential logic.
Day 3. FPGA, exercises with buttons, switches, LED, seven-segment indicator.
Day 4. FPGA, output of geometric shapes on VGA.
Day 5. FPGA, a state machine for playing tanchiki, racing or Angry Birds.

Week 2. Processor

Day 1. Programming in assembly language.
Day 2. One-cycle processor schoolMIPS.
Day 3. Integration of the processor with the output of geometric shapes on the VGA.
Day 4. Lecture about interruptions and multitasking. Individual project - a video game programmable on a video processor with output to VGA.
Day 5. Lecture about the conveyor. Competition of individual projects.

Week 3. Programmable radio. The block program consists of three main parts:

- basics of electrodynamics and radio wave propagation (theoretical part);
- principle of operation of the transmitting and receiving path (theory and practice);
- basics of digital signal processing - filtering, spectral analysis (theory and practice).

Day 1. Theoretical fundamentals of electrodynamics and radio wave propagation. Block diagram of the transmitting tract, the function of the components. Signals (harmonic, rectangular). Signal Exercise with NI Elvis.
Day 2. Transfer of signals to high frequency. Mathematical justification for frequency transfer using Matlab. Practical exercise on frequency transfer using NI Datex.
Day 3. Amplification and emission of signals. Exercise with NI Datex. Demonstration of antenna directivity.
Day 4. Signal filtering. Exercise with NI Datex. Matlab Digital Signal Filtering
Day 5. Transfer of signals to a low frequency. Exercise with NI Datex. Summary of the material covered, summing up.

By the way, much of Steven Hagg's materials, from which I look at information about sprites and so on - comes from the ancient Texas Instruments TMS9918 video processor, which stood in the Japanese computer Yamaha MSX, which was imported by the Gorbachev government for computerization of Soviet schools. When I was a schoolboy myself, even managing this video processor from the assembler program running on the Zilog Z80 main processor was nontrivial, and to design this video processor in general. Due to the breakthrough of the automation technology of designing microchips (Electronic Design Automation - EDA), this has become possible for modern schoolchildren, and even useful for learning the design of modern chips (Stephen Hagg’s book - 2018).

But for the now gray-haired Soviet schoolchildren - do you remember this game on the Yamaha?


About Electronic Design Automation. In addition to the camp for schoolchildren, we are here with Elizabeth helping to hold a seminar on similar topics for adults, but not in Zelenograd, but in Las Vegas, at the Design Automation Conference - DAC , and not with educational, but with industrial processors, and not graphics, and with a coprocessor for AI. Such a seminar is a natural next step for schoolchildren who will attend school in Zelenograd and then study at MIET, MEPI, MIPT, HSE MIEM, MSU, ITMO, LETI, SSAU, NSTU and other universities that teach RTL- to-GDSII, computer architecture and synthesis labs for FPGA / FPGA.

Source: https://habr.com/ru/post/453760/


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