Hardware components of the onboard MPS of the unified F-35 strike fighter

The priorities of modern military aviation are focused on high-quality situational awareness, so the modern fighter is a flying swarm of high-tech sensors. Information is collected from these sensors, processed and presented to the user by an on-board microprocessor system (MPS). Yesterday, HPEC hybrids (including CPU, GPU and FPGA) were used to implement it. Today, single-chip SoC-systems are used for its implementation, which, besides the fact that all components are assembled for one chipset, they also organize an intrachip network (NoC) as an alternative to the traditional data transmission line. Tomorrow, when SoC-systems become even more mature, the arrival of polymorphic nanoelectronics is expected, which will give a significant performance increase and reduce the rate of its moral obsolescence.

Introduction

If in the 4th generation fighter era, the indicators of combat superiority were high speed and economical power consumption, in the 5th generation fighter era, combat superiority is measured primarily by the quality of situational awareness. [6] Therefore, a modern fighter is a flying swarm of all sorts of high-tech sensors, providing a total of "360-degree situational awareness." [5] The collection of information from these sensors, its processing and a view that is palatable to the pilot, require enormous computing power.

All these calculations need to be done on board, since the total intensity of the input data stream from the entire swarm of sensors (video cameras, radar, ultraviolet and infrared sensors, lidar, sonar, etc.) exceeds the throughput of external high-speed communication channels by at least 1000 times. [2] Onboard signal processing is also attractive because it helps the pilot to get relevant information in real time.

The “digestibility of the presentation” means that all information, no matter how heterogeneous it is, should be synthesized into a single “theatrical picture of the fighting”, [9] the interpretation of which should not turn into a puzzling analytical task (as it was in the old models of fighters, where the pilot had to simultaneously watch a dozen displays).

High performance integrated system

Responsibility for this theatrical production, or speaking more formally, the responsibility for solving this complex and difficult task lies on the on-board MPS, which, in addition to high performance, must also provide a fairly low level of SWaP (dimensions, mass, and power consumption), which is an "evergreen problem ". [8] Today, a popular (but not the most advanced) solution in this regard is the use of three processors of different types located in one package: CPU, GPU and FPGA. The well-known name of such a hybrid is HPEC (high-performance integrated system). [2] The key to its, hybrid, successful implementation is the thought-out architecture of the IPU, which takes the best characteristics from each processor and bypasses their weaknesses. At the same time, the goal of the HPEC architecture is to achieve a synergy effect — when the performance of the final hybrid system far exceeds the total performance of its component parts. So hybrid architecture combines several different types of processors in a single package. The idea is that if you use the strengths of each individual component, you can build an advanced HPEC system that marries a stunning performance, and their child will be a baby-SWaP. [10] Let us consider in more detail each of the three components of the HPEC architecture.

HPEC hybrid example

The advantage of an FPGA is that it implements algorithms in hardware, and such an implementation, as is well known, is always faster. In addition, working at relatively low clock frequencies of the order of hundreds of MHz, FPGAs can produce tens of thousands of computations per clock and at the same time consume much less power than the GPU. It is difficult to compete with FPGAs also in response time (hundreds of nanoseconds versus a dozen microseconds that a GPU can provide). It is also worth noting that modern FPGAs have the ability to dynamically reconfigure: they can be reprogrammed on the fly (without rebooting and stopping) - in order to adapt the algorithms to changing operating conditions. Therefore, FPGA (for example, Xilinx) is good for preprocessing incoming data from sensors. It sifts the raw information coming from sensors and transfers further more compressed useful flow. FPGA is irreplaceable here, because a homogeneous data stream, processing of which is also easy to parallelize, is the task where FPGA is the leader of the genre.

FPGAs are currently the core of the most critical subsystems of military aviation’s onboard MPS: on-board control computer, navigation system, cockpit displays, brake systems, temperature and pressure regulators in the cabin, lighting devices, aircraft engine control units. [14] FPGAs are also the core of onboard network communications, electro-optical guidance systems and other types of intensive resource-intensive computing for “integrated avionics modules” (IMA) on board a “unified impact fighter” (JSF), such as the F-35. [five]

GPU (for example, Nvidia Tesla) is good for parallel processing of algorithms with intensive mathematics and floating point. It does it better than FPGA and CPU. The massive parallel design of the graphics processor, consisting of several hundred cores, allows you to process parallel algorithms much faster than the CPU. FPGA is of course also good at parallel processing, but not where it’s about floating point operations. FPGA alone cannot do them, whereas a modern GPU provides a trillion floating point operations per second — which, for example, is very useful for such tasks as stitching several gigapixel video streams.

A multi-core CPU (for example, Intel Core i7) is good for cognitive processing.

So, taking the best performance of all processors and bypassing their weaknesses, you can achieve outstanding computing power. In addition, to achieve even higher performance, other specialized processors may be included in HPEC. For example, to solve problems of an onboard navigation system, PPU (Physics Processing Unit), a hardware accelerator of physical calculations, optimized for working with the dynamics of solid, liquid and soft bodies, for collision detection, for analyzing finite elements, for analyzing fractures of an object and etc. [11] Other examples of specialized processors are a hardware accelerator of radar signal processing [1] and a hardware accelerator for analyzing graphs, [12] which will be indispensable for processing “big data”. In the foreseeable future, due to the cheapening of hardware and simplifying the process of their development, a variety of hardware accelerators are expected to appear that will replenish the “periodic computational system of primary elements”, [10] which will make the alchemical engineering design process even more effective.

Shrinking MPS on one chipset

So, we looked at the HPEC architecture, which is capable of providing high performance with a fairly low level of SWaP. However, in this respect there is a more advanced solution: the concept of SoC, the essence of which is to place the entire microprocessor system - on a single chipset . SoC combines the programmability of the processor and the configurability of the FPGA hardware, providing an unrivaled level of system performance, flexibility and scalability.

A significant shift in this regard in the direction of the software component - makes it possible to create multifunctional systems with ever-increasing capabilities and an ever-decreasing size and cost. The use of reprogrammable components also allows for cheaper and faster updates of outdated systems - without the need to update the hardware with each incremental improvement of their architecture, which is especially important for the military industry.

A typical SoC system includes:

• microcontroller, multi-core CPU, or DSP core;
• memory blocks, with a choice: ROM, RAM, EEPROM and flash;
• timers - including generators and phase locked loops;
• peripheral devices, including counter-timers, real-time timers, turn-on and reset generators;
• external interfaces, including common ones: USB, FireWire, Ethernet, USART, and SPI;
• analog interfaces, including D / A converters and ADC blocks;
• voltage regulators and power management schemes;
• data buses, through which all the above blocks exchange information;
• DMA controllers located between external interfaces and memory, which allow you to exchange data without going through the processor core, thereby increasing the SoC throughput.

The new trend in such a large-scale SoC integration, the last straw for the emergence of which was the growing popularity of eight-core processors, is the “intrachip network” (NoC). This concept proposes to abandon the traditional data transmission buses, and replace them with an intrachip network . For example, Arteris Inc uses the NoC concept to manage intrachip traffic and exchange control signals, resulting in a significant increase in throughput. [7]

Architecture of SoC-system from Arteris Inc

Conclusion

Summing up the review of high-performance systems in general, and SoC in particular, - as their representative most popular today - we can say that the evolution of the small form factor of embedded computing systems took place so quickly, and its influence on the architecture and capabilities of the system is so extensive. It may take years for design engineers to integrate this cutting-edge single chip concept into their solutions. In addition, since the efforts to develop SoC-systems are largely aimed at ensuring that the hardware becomes obsolete as slowly as possible, they tend to have a predominance of reprogrammable components. Therefore, there is reason to believe that tomorrow's nanoelectronics will be able to complete user customization, with the result that the border between hardware and software design will be completely erased. [7] In fact, such an event marks the beginning of a new era — polymorphic nanoelectronics, which combines such contradictory characteristics as software flexibility and high performance hardware acceleration. This will allow developers to take only the best features from existing software and hardware architectures, and their weaknesses are not something to ignore (as is done when designing an HPEC architecture), and in principle not to include them in the final design of the device. At the same time, the probability of achieving the synergy effect (which was discussed in the discussion of the HPEC architecture) is significantly increased. What will undoubtedly play a key role in improving the quality of situational awareness, which, as stated at the beginning of the article, is today the key to combat superiority. Not only in the airspace, but also in the rest of the "theater of operations".