Additional Uplinks in the Intel C620 system logic architecture
In the architecture of x86 platforms, two currents arose, mutually complementing each other. According to one version, it is necessary to move towards integration of computing and control resources in one chip. The second approach professes the distribution of duties: the processor is equipped with a productive bus that forms a peripheral scalable ecosystem. It forms the basis of the Intel C620 system logic topology for high-level platforms.
The principal difference from the previous Intel C610 chipset is the expansion of the communication channel of the processor with the peripherals included in the PCH chip by using PCIe links along with the traditional DMI bus.
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Let us consider in more detail the innovations of the south Intel Lewisburg bridge: what evolutionary and revolutionary approaches have its powers extended in communication with processors?
As part of an evolutionary approach, the main communication channel of the CPU with the south bridge, which is the DMI (Direct Media Interface) bus, received support for PCIe x4 Gen3 mode with a performance of 8.0 GT / S. Previously, on the Intel C610 PCH, processor and system logic communication was performed in PCIe x4 Gen 2 mode in the 5.0 GT / S bandwidth.
Intel C610 and C620 system logic functionality comparison
Note that this subsystem is much more conservative than the embedded PCIe ports of the processor, commonly used to connect GPU and NVMe drives, where PCIe 3.0 has been used for a long time and the transition to PCI Express Gen4 is planned.
By the revolutionary changes include the addition of new PCIe-channels of communication CPU-PCH, called Additional Uplinks. Physically, these are two PCI Express ports operating in PCIe x8 Gen3 and PCIe x16 Gen3 modes, both are 8.0 GT / S.
For interaction between the CPU and the Intel C620 PCH, 3 buses are used: DMI and two PCI Express ports
What was the reason for the revision of the existing topology of communications with the Intel C620? First, PCH can integrate up to 4x 10GbE network controllers with RDMA functionality. Secondly, a new and faster generation of Intel QuickAssist Technology (QAT) co-processors is responsible for encrypting network traffic and sharing with the storage subsystem, providing hardware support for compression and encryption. And finally, the “engine of innovation” is the Innovation Engine , which will be available only to OEMs.
An important feature is the ability to optionally select not only the PCH connection topology, but also the priorities of the internal resources of the chip in accessing high-speed communication channels with the central processor (s). In addition, in a special EPO (EndPoint Only Mode) mode, PCH is connected in the status of a regular PCI Express device containing 10 GbE and Intel QAT resources. At the same time, the classic DMI interface, as well as a number of Legacy subsystems, shown in black in the diagram, are disabled.
Intel C620 PCH Internal Architecture
Theoretically, this makes it possible to use more than one Intel C620 PCH chip in the system, scaling the functionality of 10 GbE and Intel QAT in accordance with the performance requirements. At the same time, the Legacy functions, which are needed only in a single copy, can only be included on one of the installed PCH chips.
So, the final word in the design will belong to the platform developer, acting on the basis of both technological and marketing factors in accordance with the positioning of each specific product.
The principal difference from the previous Intel C610 chipset is the expansion of the communication channel of the processor with the peripherals included in the PCH chip by using PCIe links along with the traditional DMI bus.
')
Let us consider in more detail the innovations of the south Intel Lewisburg bridge: what evolutionary and revolutionary approaches have its powers extended in communication with processors?
Evolutionary changes in communication CPU-PCH
As part of an evolutionary approach, the main communication channel of the CPU with the south bridge, which is the DMI (Direct Media Interface) bus, received support for PCIe x4 Gen3 mode with a performance of 8.0 GT / S. Previously, on the Intel C610 PCH, processor and system logic communication was performed in PCIe x4 Gen 2 mode in the 5.0 GT / S bandwidth.
Intel C610 and C620 system logic functionality comparison
Note that this subsystem is much more conservative than the embedded PCIe ports of the processor, commonly used to connect GPU and NVMe drives, where PCIe 3.0 has been used for a long time and the transition to PCI Express Gen4 is planned.
Revolutionary changes in communication CPU-PCH
By the revolutionary changes include the addition of new PCIe-channels of communication CPU-PCH, called Additional Uplinks. Physically, these are two PCI Express ports operating in PCIe x8 Gen3 and PCIe x16 Gen3 modes, both are 8.0 GT / S.
For interaction between the CPU and the Intel C620 PCH, 3 buses are used: DMI and two PCI Express ports
What was the reason for the revision of the existing topology of communications with the Intel C620? First, PCH can integrate up to 4x 10GbE network controllers with RDMA functionality. Secondly, a new and faster generation of Intel QuickAssist Technology (QAT) co-processors is responsible for encrypting network traffic and sharing with the storage subsystem, providing hardware support for compression and encryption. And finally, the “engine of innovation” is the Innovation Engine , which will be available only to OEMs.
Scalability and flexibility
An important feature is the ability to optionally select not only the PCH connection topology, but also the priorities of the internal resources of the chip in accessing high-speed communication channels with the central processor (s). In addition, in a special EPO (EndPoint Only Mode) mode, PCH is connected in the status of a regular PCI Express device containing 10 GbE and Intel QAT resources. At the same time, the classic DMI interface, as well as a number of Legacy subsystems, shown in black in the diagram, are disabled.
Intel C620 PCH Internal Architecture
Theoretically, this makes it possible to use more than one Intel C620 PCH chip in the system, scaling the functionality of 10 GbE and Intel QAT in accordance with the performance requirements. At the same time, the Legacy functions, which are needed only in a single copy, can only be included on one of the installed PCH chips.
So, the final word in the design will belong to the platform developer, acting on the basis of both technological and marketing factors in accordance with the positioning of each specific product.
Source: https://habr.com/ru/post/451758/
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