Apple’s electronics engineer’s departure caused a flurry among speculators. How to become like him?

On March 29, an engineer named Gerard Williams the Third left Apple. This news was immediately published by CNET and another three dozen publications all over the world, not only technical, but also financial. What did this engineer do that caused his departure to cause excitement among stock speculators? For 9 years he designed processors at Apple iPhone, before that he worked at ARM for 12 years, before that he designed DSP at Texas Instruments, and before that he had developed FPGA circuits at Intel. In all places, he used design technology at the register transfer level, using Verilog and VHDL hardware description languages.

Examples closer to Russia? The photo on the right: 25-year-old Muscovite Ilya Neganov picked up the Harris & Harris book in 2011 (the latest version of which can be downloaded here or here ), designed a simple processor, now works for Apple, designs on the GPU chain, flies on weekends on a small plane. Below are a couple of newlyweds from St. Petersburg, who designed on the chain and FPGA image processing from the camera and received a prize at the Innovate FPGA competition. They spent their honeymoon at Intel’s headquarters in Santa Clara. Then comrades from Kiev, two of whom won bronze at the European Final of Innovate FPGA. And finally, two schoolchildren, from classes 5 and 9, who do their first exercises with microcircuits of a small degree of integration on a breadboard, then proceed to exercises on the logic board and FPGAs.

These are five points on the trajectory from the schoolboy to Gerard Williams the Third. The trajectory is quite heavy, since the initial barrier to entering the design of digital microcircuits is higher than that to entering programming. In this post we will talk about how to facilitate the initial part of the trajectory for Russian and other schoolchildren.
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During these two weeks, a group of colleagues from RUSNANO, Wave Computing, MIET, IVA Technologies, HSE MIEM, Amperka, DMK-Press Publishers conducts the following event: First, students take a theoretical online course (parts “From Transistor to Microchip” , “Logical Side of Digital circuit design " , " The physical side of digital circuit design " ), where they become acquainted with the so-called route RTL2GDSII - a group of technologies that are used by engineers in electronic companies to design chips. Then we conduct practical classes with FPGA reconfigurable logic chips . In this way, for example, MIT teaches 6.111, but we try it in a very basic form for schoolchildren of the Olympiad type.

The theoretical course is important not to waste time on a practical course to explain the design theory at the register transfer level, but simply to spend three evenings for two hours playing with the FPGA boards, which you can then take with you. Also, the theoretical course links exercises with FPGAs to mass products that use ASIC chips.

The practical course will be another experiment (previous ones were conducted by different teachers in Nizhny Novgorod, Kiev, Almaty, Kazakhstan, Minsk, Novosibirsk, Tomsk and Irkutsk) to figure out how to do exercises with Verilog and FPGA interesting and useful for beginners.

Should I do exercises with microcircuits of a small degree of integration before exercises with FPGA? There are different opinions on this point: Dean of the Samara University Ilya Kudryavtsev believes that it is not worth it, it is better to immediately present modern technology in 2019, and not the ancient CMOS 4000 on the breadboard, which were relevant 50 years ago. Neurochip design engineer at IVA Technologies Stanislav Zhelio thinks he is worth it, because otherwise students perceive FPGA as just another microcontroller of the Arduino type, but just with a strange Verilog programming language. In fact, a student or a school student should immediately realize that the verification file describes the scheme, not the program (chain of instructions), and the exercises with CMOS 4000 help settle the correct image in the brain.

If you write on Verilog as if it were a program, not a circuit, then the code will work on the simulator, but will not be synthesized, and even if it is synthesized, you will get a crazy (in terms of timing or size) circuit.

Therefore, one of the approaches is as follows: to design a circuit on chips with a small degree of integration (counters, shift registers, adders, decoders), then repeat it on the verilogue, synthesize and write to the FPGA.

Some say: why not draw a diagram for the FPGA with a mouse on the screen (schematic entry) and enter it into the FPGA before doing the exercises on the chain? The mouse approach has three drawbacks:

1. It requires learning software, which is longer than just sticking components into a breadboard.
2. Experience from a burnt-out LED or a floating input without a pull-up resistor on a breadboard is more valuable than a sterile experience in a schematic entry.
3. Digital logic designers have not used schematic entry since the early 1990s, they all write on the chain, sometimes on VHDL.

Yes, CMOS 4000 and 74XX became obsolete in the 1970s, they were replaced by PAL, GAL, PLD, then integrated chips. Therefore, in the 1970s, they were used in circles for children, and in the 1980s they went out of fashion, because they stopped paying salaries for the ability to use them, but no one has since figured out how to demonstrate, for example, the D-flip-flop function, so as a prequel to the FPGA / FPGA you can apply them. MIT is doing the same - see Lab # 1 here .

After the exercises with microcircuits of a small degree of integration and their equivalents on the chain on the FPGA, you can complicate the tasks and do on one FPGA something that required dozens, hundreds or thousands of microcircuits of a small degree of integration, which I will discuss later.

Here is an example of combinational logic, a priority encoder, on chips with a small degree of integration:


And this is what this priority encoder looks like in the Verilog hardware description language:

module priority_encoder
(
    input      [2:0] in,
    output reg [1:0] out
);

    always @*
    begin
        casez (in)
            3'b1??  : out = 2'd1;
            3'b01?  : out = 2'd2;
            3'b001  : out = 2'd3;
            default : out = 2'd0;
        endcase
    end

endmodule

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