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Intel PAC with FPGA Stratix 10 SX - an accelerator for large tasks


FPGA Intel Stratix 10 SX / GX , which appeared on sale 2 years ago, became a new word in the field of gate arrays. Made on the minimum at the time 14-nm process technology, they were twice as productive and 70% more efficient than their predecessors. However, to realize all the capabilities of Intel's FPGA, we need the same advanced wrapper. The hardware / software construct released by Intel for using Stratix in host systems is called the Programmable Acceleration Card (PAC) - its latest version was announced in September of this year.

The new PAC is based on the FPGA Intel Stratix 10 SX - the most powerful model from the Stratix 10 family. Let me recall in brief its main characteristics:


As for the Programmable Acceleration Card itself, its functional device is as follows.


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The same in more detail as a table.

Form factorPCIe Gen3 x16
Full height, 3/4 length, dual slot
Memory32 GB DDR4 (4x8 GB) ECC
Network interfaces2X QSFP + up to 100 Gbps
Service interfaceUSB 2.0 for debugging and programming
Control controllerIntel MAX 10 FPGA Baseboard Management Controller (BMC)
• Read temperature and voltage data
• Platform Level Data Model (PLDM)
• IPMI 2.0
Power managementIntel Enpirion Power Solutions (real-time telemetry and status monitoring)
Software• Acceleration Stack for Intel Xeon CPU with FPGA
• FPGA Interface Manager
• Intel Quartus Prime Pro Edition
• Intel FPGA SDK for OpenCL
The card will be available as part of Intel OEM partners (in particular, Hewlett Packard Enterprise) at the beginning of next year.

Source: https://habr.com/ru/post/425187/


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