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To systems on a chip through FPGAs: the week of digital microelectronics in Kiev - April 24-29, 2017


On April 24-29, Kiev will host a series of seminars for schoolchildren who do not look like regular classes with embedded processors that use Lego / Arduino / Rasberry Pie as standard. The main focus of the seminars is not to teach how to program processors, but to show principles how processors are designed inside. It's like the difference between “learn to drive a car” and “teach how to design an engine.” At the seminars, students will use the language of the description of the device Verilog and logic synthesis - technologies that are used by developers of digital microcircuits in Apple, Samsung and other electronic companies.

The main official page of the seminar, the same registration .

For exercises, FPGA boards are used - matrices of logic elements with variable function (this is not the usual “processor + memory”). FPGAs have long been used to teach students to design electronics at Stanford and MIT, and more recently in Russian and Ukrainian universities. Using FPGAs for teaching schoolchildren is an experiment, and you have a chance to participate in it. To facilitate entry into Verilog and FPGA, we will first take up exercises with small-scale integrated circuits on bezpeechnyh development boards. Then we will deal with the FPGA and on the last day of the seminars we will compare the FPGA design with the programming of the microprocessor for the Internet of things.

You will finally see what happens between the transistor and the Arduino, in an area where schoolchildren rarely drop in!
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Program for older students and younger students



Monday April 24th. Getting the path to the FPGA: combinational logic and binary arithmetic on chips of low degree of integration
Location: Belka Student Space KPI




Tuesday April 25th. We add memory: Sequential logic on chips of low degree of integration.




Wednesday April 26th. Combination logic and binary arithmetic on Verilog and FPGA.
Location: Belka Student Space KPI.


An example of code in the Verilog hardware description language, which is translated (synthesized) into the schema:

module counter ( input clock, input reset_n, output reg [31:0] count ); always @(posedge clock or negedge reset_n) begin if (! reset_n) count <= 32'b0; else count <= count + 32'b1; end endmodule //---------------------------------------------------------------------------- module seven_segment_display_driver ( input [3:0] number, output reg [6:0] abcdefg ); // abcdefg dp    // 7 6 4 2 1 9 10 5  7-  // 7 6 5 4 3 2 1   pio   // --a-- // | | // fb // | | // --g-- // | | // ec // | | // --d-- always @* case (number) 4'h0: abcdefg = 7'b1111110; 4'h1: abcdefg = 7'b0110000; 4'h2: abcdefg = 7'b1101101; 4'h3: abcdefg = 7'b1111001; 4'h4: abcdefg = 7'b0110011; 4'h5: abcdefg = 7'b1011011; 4'h6: abcdefg = 7'b1011111; 4'h7: abcdefg = 7'b1110000; 4'h8: abcdefg = 7'b1111111; 4'h9: abcdefg = 7'b1111011; 4'ha: abcdefg = 7'b1110111; 4'hb: abcdefg = 7'b0011111; 4'hc: abcdefg = 7'b1001110; 4'hd: abcdefg = 7'b0111101; 4'he: abcdefg = 7'b1001111; 4'hf: abcdefg = 7'b1000111; endcase endmodule //---------------------------------------------------------------------------- module top ( input CLK, //   12 MHz inout [48:1] pio // GPIO, General-Purpose Input/Output ); wire reset_n = ! pio [8]; wire [31:0] count; counter counter_i ( .clock ( CLK ), .reset_n ( reset_n ), .count ( count ) ); seven_segment_display_driver display_driver_i ( .number ( count [26:23] ), .abcdefg ( pio [ 7: 1] ) ); endmodule 

Thursday April 27th. Sequential logic and finite automata on Verilog and FPGA.
Location: Belka Student Space KPI.




Friday April 28th. Comparison of circuit design with embedded microprocessor programming.
Location: Belka Student Space KPI.




Saturday April 29th. Hackathon
Place: National University "Kyiv-Mohyla Academy"




Program for younger students

April intensive "Introduction to Electronics"
Monday April 24th. Familiarity with the basics: Ohm's law, passive electronic elements (resistors and capacitors)
Venue: Office of Radiomag Ukraine LLC, Chokolovsky Boulevard, 42-A
Time: 17: 00-19: 00
Lecturer: Sergey Chenash


Tuesday April 25th. Active electronic components: the structure and principles of operation of diodes and transistors
Venue: Office of Radiomag Ukraine LLC, Chokolovsky Boulevard, 42-A
Time: 17: 00-19: 00
Lecturer: Sergey Chenash


Thursday April 27th. Studies of the elements of optoelectronics: LEDs, photoresistors, phototransistors, optocouplers
Venue: Office of Radiomag Ukraine LLC, Chokolovsky Boulevard, 42-A
Time: 17: 00-19: 00
Lecturer: Sergey Chenash


Friday April 28th. Introducing the NE555 Chip
Venue: Office of Radiomag Ukraine LLC, Chokolovsky Boulevard, 42-A
Time: 17: 00-19: 00
Lecturer: Sergey Chenash


Saturday April 29th. Bonus rations
Venue: Office of Radiomag Ukraine LLC, Chokolovsky Boulevard, 42-A
Time: 11: 00-12: 30



See you at the seminars!


The main official page of the seminar, the same registration .

Source: https://habr.com/ru/post/403267/


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