Every novice radio amateur paid attention to additional loops of unknown purpose on printed circuit boards. Why bend the track, create additional interference, if it is more rational to make the track straight?





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Why bend the track?

The speed of the electrical signal is equal to the speed of light. There is nothing faster than this. In a second the electric signal passes 299 792 458 meters! It is almost like from Earth to the Moon. It would seem - where does our little tracks? Let's take a look at the levels of any data bus.





Fig. 1. SPI bus signal levels



In the diagram, the period of one cycle of the clock signal is indicated by the letter T. Let's calculate its length if the bus speed (and the clock signal frequency in this case) = 1 MHz.



299,792,458 m / 1,000,000 times = 299.79 meters.



There is nothing to worry about yet. Now imagine that the bus frequency = 2GHz. Then the length of the period of one clock cycle is 15 cm. For clarity, we give an example of this: we split the board and the clock track length was 4 cm, and the track length was 20 cm. This means that when the first clock cycle ends at the end of the clock track , the signal on the data track will be on the way.





Fig. 2. The passage of signals along the tracks



In this example, in the first bit, we sent 1. The clock track worked a cycle and the second bit began. At the same time, the unit has not reached the data track. If the data is recognized at the rising edge (that is, when the clock transitions from 0 to 1), then the second bit is also obtained = 0, since 1 from the first bit has not yet reached and at the end of track 0. We only see our 1 in third bit! If the data is recognized at the falling edge of the clock signal, then we will see in the second bit the one from the first bit.



Hence the conclusions:

1. to identify data at the rising edge of a clock signal, the data track must be the same length or shorter than a maximum of half a cycle of the clock signal.
2. in order to identify data with a falling edge of a clock signal, the data track must be the same length or longer than a maximum of half a cycle of a clock signal.

The admission in the half-period is conditionally taken, since it still needs to take into account the speed of the receiving chip. That is, the tolerance is less.



Tolerance (either upper or lower) = 299 792 458 / (2 * Tact_signal frequency) - 299 792 458 / speed_switching_port_ receiver_.



If the path is located between two continuous conductive layers, then the resulting tolerance must be halved (for PCB).

Sometimes the specifications clearly indicate the tolerance for difference in track length.