Released the first Russian distribution of free OS Tizen
On the portal for developers of the Tayzen OS, the binary files of the first distribution of the free operating system Tizen for the domestic processor 1892BM14YA of RPC ELVIS were published.
The 1892BM14Y processor is the only chip in Russia that is most suitable for replacing the NXP i.MX6 (formerly Freescale), Texas Instruments DaVinci and TMS320C6000 series, as well as Allwinner, Rockchip and MediaTek in the import substitution program.
The developers believe that having your own processor and operating system reduces the risks in case of a ban on the supply of imported components. This is true for state-owned companies and the army of the Russian Federation, which will have to use mobile devices of domestic production.
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At the beginning of June, the first working prototype based on the Salyut-EL24D1 debugging module and Tizen OS was presented at the Skolkovo Startup Village conference at the stand of the Association “Taizen.Ru” (in the photo).
The Salyut-EL24D1 debugging module is designed to study the hardware and software tools of the 1892BM14I microprocessor, debug user applications, prototype intelligent control systems, digital signal processing, input / output and video processing.
The prototype of a single-board computer with a Russian processor aroused the interest of the Chinese comrades who attended the conference.
1892BM14I processor
The low-power multi-core signaling microprocessor 1892BM14Ya is designed for communication, navigation, multimedia, embedded, mobile applications, including tablets, smart video cameras, telephones.
It is a high-performance microprocessor system on chip, including two ELcore-30M DSP cores, two ARM Cortex-A9 CPUs, H.264 codec, Mali-300 graphic 3D accelerator, GLONASS / GPS / Beidou navigation correlator and built-in I / O ports.
Technical characteristics 1892VM14YA
Manufacturing technology - CMOS, 40LP TSMC process.
Architecture: multi-core heterogeneous "system-on-chip" using IP blocks of the MULTIKOR platform (from OAO NPC ELVIS) and purchased IP blocks.
Maximum operating frequency:
912 MHz CPU / 720 MHz DSP under normal conditions;
not less than 744 MHz CPU / 480 MHz DSP for the worst conditions;
1104 MHz CPU / 912 MHz DSP under normal conditions and increased core voltage (1.2V).
Total microprocessor consumption:
common type - 3 W (depending on the resources used);
in hibernation mode - up to 130 mW;
in deep sleep mode - 75 mW;
DSP consumption - 0.5 Ă· 0.8 mW / MHz (depending on the task) per core;
CPU consumption - 0.3 Ă· 0.5 mW / MHz (depending on the task) per core;
power management system.
Power supply voltage:
core supply voltage: 1.1–1.2 V;
adjustable peripheral supply voltage: 1.8 / 2.5 / 3.3 V.
Multicore heterogeneous MIMD-architecture based on standard processor and specialized cores:
Standard Controlled Dual Core - Dual CORTEX-A9 (PU 0-1) with FPU-accelerator and NEON SIMD-accelerator (ARM);
cluster based on two DSP-cores with floating and fixed point ELCore-30M; full software compatibility with microcircuits 1892VM10Ya, 1892VM15F;
graphic 2D / 3D accelerator (MALI-300, ARM); support for OpenVG 1.1, OpenGLES 2.0 / 1.1; resolution support up to HD 1080p with 4x anti-aliasing; built-in 8 KB second-level cache; 250 million pixels / s;
the core of the multichannel GLONASS / GPS / BeiDou-correlator;
VELcore-01 video codec: providing H.264 CBP Encode and Decode functions, Full HD (1920x1080) stereo stream with a repetition rate of at least 30 frames / s; 1 MB VRAM video data memory available for CPU and DSP;
hardware accelerator for JPEG image compression.
Periphery:
Ethernet MAC controller 10/100/1000;
two DDR3 ports; maximum data transfer rate of 1066 Mbit / s at a frequency of 533 MHz; digit capacity - 16/32;
NORMPORT memory port for connecting the SRAM / PSRAM / ROM / NOR FLASH memory;
NANDMPORT memory port for connecting a NAND FLASH memory;
two SD / MMC ports with support for SD3.0 / MMC4.5;
two multifunctional MFBSP ports (LPORT, SPI, I2S, GPIO) with DMA;
four universal asynchronous ports (UART) type 16550A;
USB2.0 (HOST + DEVICE + PHY), 480 Mbit / s;
“Intelligent” multi-channel SDMA DMA controller;
DMA controller with the ability to directly process requests for PDMA peripherals;
128 multiplexed GPIO outputs; the ability to enter 32 external interrupts;
three I2C interface ports;
Two dedicated SPI ports;
dedicated port interface I2S;
four built-in PWM modulators;
two SpaceWire ports to provide the network capabilities of the chip; Comply with ECSS-E-50-12C; data transmission and reception speeds - from 2 to 400 Mbit / s; duplex operation;
eight universal 32-bit timers, interval / real time (IT / RTT);
32-bit watchdog timer (WDT);
real-time timer (RTC); full calendar support: seconds, minutes, hours, days, months, years; external synchronization - 32.768 kHz;
Extensive debugging and tracing capabilities: ARM CoreSight debugging and tracing architecture; IEEE1149.1 (JTAG) debugging; DAP debug port with access to the internal memory of the chip;
two video input ports:
MIPI CSI port or parallel port;
built-in DMA;
built-in Image Preprocessor.
video output port:
MIPI DSI port or parallel port;
built-in DMA.
power management controller: power on and off control; formation and storage of real time.
Case type: 1296 HFCBGA, 19 mm x 19 mm, lead pitch 0.5 mm.
Architecture: multi-core heterogeneous "system-on-chip" using IP blocks of the MULTIKOR platform (from OAO NPC ELVIS) and purchased IP blocks.
Maximum operating frequency:
912 MHz CPU / 720 MHz DSP under normal conditions;
not less than 744 MHz CPU / 480 MHz DSP for the worst conditions;
1104 MHz CPU / 912 MHz DSP under normal conditions and increased core voltage (1.2V).
Total microprocessor consumption:
common type - 3 W (depending on the resources used);
in hibernation mode - up to 130 mW;
in deep sleep mode - 75 mW;
DSP consumption - 0.5 Ă· 0.8 mW / MHz (depending on the task) per core;
CPU consumption - 0.3 Ă· 0.5 mW / MHz (depending on the task) per core;
power management system.
Power supply voltage:
core supply voltage: 1.1–1.2 V;
adjustable peripheral supply voltage: 1.8 / 2.5 / 3.3 V.
Multicore heterogeneous MIMD-architecture based on standard processor and specialized cores:
Standard Controlled Dual Core - Dual CORTEX-A9 (PU 0-1) with FPU-accelerator and NEON SIMD-accelerator (ARM);
cluster based on two DSP-cores with floating and fixed point ELCore-30M; full software compatibility with microcircuits 1892VM10Ya, 1892VM15F;
graphic 2D / 3D accelerator (MALI-300, ARM); support for OpenVG 1.1, OpenGLES 2.0 / 1.1; resolution support up to HD 1080p with 4x anti-aliasing; built-in 8 KB second-level cache; 250 million pixels / s;
the core of the multichannel GLONASS / GPS / BeiDou-correlator;
VELcore-01 video codec: providing H.264 CBP Encode and Decode functions, Full HD (1920x1080) stereo stream with a repetition rate of at least 30 frames / s; 1 MB VRAM video data memory available for CPU and DSP;
hardware accelerator for JPEG image compression.
Periphery:
Ethernet MAC controller 10/100/1000;
two DDR3 ports; maximum data transfer rate of 1066 Mbit / s at a frequency of 533 MHz; digit capacity - 16/32;
NORMPORT memory port for connecting the SRAM / PSRAM / ROM / NOR FLASH memory;
NANDMPORT memory port for connecting a NAND FLASH memory;
two SD / MMC ports with support for SD3.0 / MMC4.5;
two multifunctional MFBSP ports (LPORT, SPI, I2S, GPIO) with DMA;
four universal asynchronous ports (UART) type 16550A;
USB2.0 (HOST + DEVICE + PHY), 480 Mbit / s;
“Intelligent” multi-channel SDMA DMA controller;
DMA controller with the ability to directly process requests for PDMA peripherals;
128 multiplexed GPIO outputs; the ability to enter 32 external interrupts;
three I2C interface ports;
Two dedicated SPI ports;
dedicated port interface I2S;
four built-in PWM modulators;
two SpaceWire ports to provide the network capabilities of the chip; Comply with ECSS-E-50-12C; data transmission and reception speeds - from 2 to 400 Mbit / s; duplex operation;
eight universal 32-bit timers, interval / real time (IT / RTT);
32-bit watchdog timer (WDT);
real-time timer (RTC); full calendar support: seconds, minutes, hours, days, months, years; external synchronization - 32.768 kHz;
Extensive debugging and tracing capabilities: ARM CoreSight debugging and tracing architecture; IEEE1149.1 (JTAG) debugging; DAP debug port with access to the internal memory of the chip;
two video input ports:
MIPI CSI port or parallel port;
built-in DMA;
built-in Image Preprocessor.
video output port:
MIPI DSI port or parallel port;
built-in DMA.
power management controller: power on and off control; formation and storage of real time.
Case type: 1296 HFCBGA, 19 mm x 19 mm, lead pitch 0.5 mm.
Integrated circuit 1892VM14Ya. Summary (pdf)
Integrated circuit 1892VM14Ya. User Guide (pdf)
Linux build instruction (kernel 4.1) for 1892BM14I processor (pdf)
The microcircuit is made using CMOS technology with a minimum topological size of 40 nm elements.
Os tizen
Tizen is an open source operating system based on the Linux kernel. It is designed for smartphones, tablets, PCs and other devices and works on processors with ARM and x86 architectures. Tizen is supported by Linux Foudation and a number of large companies that are members of the Tizen Association consortium: these are OEMs (such as Intel, Samsung, Panasonic, NEC, Huawei), and cellular operators. The steering committee (Technical Steering Group) is formed by Intel and Samsung.
OS Tizen has certain advantages compared with iOS and Android. The system implements open standards Open Connectivity, such as IoTivity. Most products based on this operating system are produced by Samsung, including smartphones, televisions and devices for the Internet of things.
For example, recently, Samsung, together with the Russian GNU / LinuxCenter, announced the start of sales of the Samsung Z3 "protected smartphone" on Tizen OS in Russia. The device is certified for businesses with high security requirements.
The Samsung Z3 is a budget version of the Galaxy S III, and will cost Russian state-owned enterprises cheaper than a Russian-made OMP Yermak certified smartphone for up to $ 2,000 . But while Samsung Z3 is unlikely to pass the requirements for certification of Russian devices, while it does not use the domestic processor and the Russian operating system.
Ordinary users buy a “secure smartphone”, which, because of certification, costs much more than usual, it makes no sense.
Taizen.ru
In Russia, the operating system Tozen is promoted and maintained by the consortium Taizen.ru , which is the exclusive owner of the Russian distribution of OS Taizen. The main feature of the Russian distribution is the implementation of an integrated proprietary safety profile to meet the requirements of Russian regulators.
On this topic:
Russian distribution Astra Linux
Introducing Tizen (Intel blog on Habrahabr)
Source: https://habr.com/ru/post/395329/
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