When Analog Devices launched the AD9361 SDR transceiver in 2013, there was a real revolution in digital radio communications. There were SDRs before, but now it was possible to get everything in one chip: 2 channels for reception and 2 for transmission (with onboard 12-bit DAC and ADC) with a channel width up to 56 MHz, local generators and radio path for operation in the range from 70 (on transfer from 47) to 6000 MHz. On the out-of-the-box AD9361, almost any digital transceiver can be implemented, with the exception of probably only UWB and a beginner in gaining popularity at the 60 GHz band (but there is almost nothing to do without multi-element hardware.). It only remains to add the source / receiver of data ( as long as this is usually FPGA), external filters and LNA / PA , if the task requires it.

I finally managed to see what was inside of him and - try to look at the financial side of the production of truly innovative microelectronics with high added value.

Time to get acid

After opening - we see a chip of 4336x4730 µm in size, running ahead - the production norms are 65nm. Only the coils from the PLL (top right and left in the middle) and the fact that the masks were released in 2011 are striking, and the chip went on sale only at the end of 2013. At the click, the full resolution (72MB):
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After etching almost all layers of metal compounds, it can be seen that the overwhelming part of the microcircuit is occupied by analog blocks:



Bottom right - digital stuffing. At maximum magnification, we see rows of standard cells. The cells are, like almost everyone, “back to back”, [PFET NFET] [NFET PFET] and thus use the common vertical lines VCC and GND (food is of course supplied from the upper levels of the metal, which are no longer visible here). PFET transistors are slightly wider (as always in silicon CMOS processes). The width of the cells is 1.83 µm, which is roughly similar to the truth for a 65nm chip. The scale after the click on the full resolution in this photo and then - 24.5nm per pixel.



Blocks are scattered over the entire area of ​​the crystal, which are probably used to check the spread of the characteristics of transistors over the area of ​​the crystal, at the initial stage of screening or even working out the technical process. However, there is no access to them after the completion of the production of all levels of metallization of the final chip - there is nowhere to connect to the upper metals, and there is also no visible digital circuit like JTAG:



The arrays of capacitors are a key element in the implementation of the DAC / ADC, the identity of the capacitors in the array is crucial, then around the edges there seem to be additional dummy elements so that the edge effects of photolithography have no effect on the size / capacity.



I did not find a single SRAM array on the chip. The only regular digital structure is left on this frame, but on topology it does not look like SRAM. In general, nothing like it. There is no way to figure it out without an electron microscope.



All analog stuffing - mainly on field-effect transistors:




Well, the title picture is all that remains of the PLL inductance (with not completely finished metal and glass - which gives such colors). PLL here is the most important part. If noise or insufficient linearity of the analogue path can still be bypassed by external bodywork and digital processing, then the PLL phase noise set an absolute and irresistible limit to the quality of radio communications:

And now for the calculator

Using this chip as an example, you can roughly calculate how the financial side of a truly high-tech product looks from a bird's eye view and as a first approximation, fortunately the annual financial statements of Analog Devices are public, and we can now estimate the cost. There is always a place to find fault with the accuracy of such rough estimates, but the main thing here is the general principle (you can go deeper into details, starting with packaging and testing ...):

The area of ​​the chip is ~ 21.12 mm², the effective area of ​​the silicon wafer with a diameter of 300 mm (and only those on 65 nm) is approximately 65'000 mm². Thus, from one plate we get 3077 chips, with a yield of 50%, 1538 pieces remain. With a plate price of $ 1600 (the technology is already old) - the cost of each good crystal is $ 1.04.

NRE (Non recurring engineering) - masks (2 sets of $ 400 thousand each) and equipment - let's say $ 1 million in total. If we estimate the total production of 1000 plates (and in reality it may be more) - NRE will add $ 0.64 per chip.

Retail price for AD9361 from distributors - $ 275, wholesale from the manufacturer - $ 175.

Analog Devices costs $ 1.68 at $ 173.32 of value added! Even vertically integrated drug cartels cannot boast of such indicators! Intel, for example, also cannot boast such a value added - the cost price there is 1.5 orders of magnitude higher.

But of course there is an obvious problem - you can't just take and make an integrated SDR transceiver: we need patents that allow us to work and have been developed over the years (generally - intellectual property) - and the chip itself needs to be developed. Therefore, part of the revenue - we send to further research and development in order to release new, more advanced, products in the future.

From the report of Analog Devices for 2017, we see that with revenues of $ 5.1 billion, R & D expenses amounted to $ 968 million, and profit before taxes was $ 3.061 billion. In such a proportion of revenue and divide. Of course, in different products everything is different, but on average it will turn out like this:

Findings:

1. All this talk about whether there are 65/28/14 nm microelectronic plants in Russia or not is a piece of cake, which is almost invisible in the diagram for this particular product. Development - requires 1.5 orders of magnitude more resources than directly mass production. Therefore, to talk about production, without investing 1.5 orders of magnitude more into development, is simply self-deception. Major money is not made in production.
2. This thin production piece of the pie is not even a profit of production, but revenue. There is the same internal division: according to old technologies, on market conditions - 90% cost (mainly imports) and loan servicing, 10% profit. Those. The microelectronic plant itself is good here if it gets $ 0.25 profit on the production of this chip. Only on the latest technologies (available in units in the world), where competition is limited - profits can be significantly higher.
3. Any high-tech product - requires a maximum increase in sales (in pieces). Do not dismiss as the obvious thing. This means that you cannot only sell in one country - the products must go to the whole world, otherwise it will not be competitive. With such a low cost of production - the link between the final price of the product and sales volumes is linear. If we sell only to Russia (which, let's say, in electronics makes up 2% of the world), then we have to sell as a first approximation 50 times more expensive.
4. Sales are provided not only by a low price (which is achieved by spreading out the cost of development to a large volume), but also by “other expenses”, which are comparable to the development itself, which includes all these incomprehensible Russian souls for poor students (who won't buy anything right now) , conferences, exhibitions and contests, advertising, and much more.
5. If there are no unique IP / developments, or all this is bought / licensed already ready (as Rosnano tries to do according to the concept of pure capitalism), then you will have to be content with tiny fractions of the pie and modest profit margins (or self-deception). "Routine" microelectronic products, for example, are sold at a price of "only" 5-10x cost of production.

Thus, it is not enough to build a conditional 14nm plant for $ 10 billion. It takes about 15 times more to spend on product development for it. And then - just as much on the promotion and support, so that the product is sold worldwide. So there is still a lot of work ahead.

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