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The article describes the mode of operation of Vivado, which allows you to make changes to the project at the level of editing the netlist (hereinafter referred to as netlist). Both the ECO mode itself and some nuances that appear while working in it are described. A demo is given and a complete sequence of actions is described for obtaining a result, which anyone who is willing to be able to make sure of its efficiency. The article will be useful for "common development" for FPGA developers, and especially for those who often debug projects in the Logic Analyzer. I hope that work in this mode will be of interest to developers working with large crystals, the compilation time in which can reach hours (or even tens of hours), because in this mode the time spent on implementation can be reduced to literally a couple of minutes.

Table of contents

The article has a lot of pictures not in the spoilers (140 pieces). Please be careful if you are logging in from the phone.

Introduction

1. develop a test case that, whenever possible, contains and demonstrates all (or at least most) of the capabilities of working in ECO mode
2. implement the project;
3. explain the concept of Design Checkpoint;
4. describe the transition to the ECO mode of operation;
5. edit the netlist and get the FPGA firmware file;
6. make sure the changes are correct;
7. create a summary table of time spent on standard changes to the project and compare it with the time spent in ECO mode, as well as incremental implementation.

1. ECO: an overview

• Modification of probes and connected lines of logic analyzers (ILA - IntegratedLogicAnalyzer) when debugging a project. The user can change the set of lines connected to ILA, while avoiding complete re-implementation of the project.
• Reassignment of the chains connected to the FPGA legs. In case the project developer, circuit designer, or circuit board developer made an error in assigning the legs (for example, rx was confused with tx), and the project on the FPGA was already implemented, this way you can reassign ports in the netlist, avoiding repeated full implementation (t . e. synthesis, mapping, optimization, placement, tracing - with all the attendant costs of machine time and resources) of the project.
• Performing “what_ if?” Analysis (editing the contents of the memory, changing the functionality of the LUT, improving the timings, etc.)

2. Design Checkpoint

The design route is divided into several components:, including synthesis and implementation. The implementation in turn is divided into sub-steps: various optimizations, placement and tracing. The intermediate stages of the design route are stored in a “container”, called Design Checkpoint (DCP) [7]. This is a file with the extension ".dcp". Design Checkpoint contains:

• The current netlist (depending on the stage of the design route), including all the optimizations performed before recording the dcp file.
• The constraints imposed on the project (design constraints).

By default, Vivado creates four dcp files: one - at the stage of synthesis of the module of the top level of the project (if synthesis is performed in out-of-context mode, then for all modules that are synthesized in out-of-context, a dcp file is created) and three - at the implementation stage. These files can be found in folders:

Figure 1 - the default dcp files (1 - “postsynthesis-” and 3 - “postimplement-”: after optimization (_opt), after placement (_placed) and after tracing (_routed))

In Vivado project mode (Project Mode [8]), .dcp files are created automatically. But when working in non-project mode (Non-ProjectMode [8]), the user must ensure that the “snapshots” of the current state of the project are recorded. To do this, use the appropriate Tcl commands [9, 10] .:

write_checkpoint <file_name>.dcp read_checkpoint <file_name>.dcp 

About why, how and what files dcp should be opened, will be discussed below.

3. Development of a test project

1. Elements that are not in the original netlist or elements for which you can change the functionality. For example, to start the LED on the button - and in the original project it will light up on pressing, and in the modified one - on pressing it will go out. That is, you will need to add an inverter to the netlist that is not in the original project.
2. Items that you can change the content. For example, the truth table in the LUT or the contents of the block memory. And the change in the contents of the block memory will be more preferable here, since we will already perform the change in LUT in claim 1, when we create an additional inverter.
3. ILA - to be able to replace connected circuits with other circuits. That is, without touching ILA itself, we will try to replace the selected circuits connected to it in the initial project with others through a netlist.
4. Confused conclusions. Suppose that when designing a printed circuit board, the developer performed the pin-swap of two pins for easy wiring, without agreeing with the FPGA developer, i.e. made a mistake of confusing rx with tx UART. In ECO mode, we will have to restore the correct connection.

3.1. Project creation

Find the Vivado icon and double-click on it, a welcome window will open (fig. 2)

To create a new project, click the Create Project button. Pressing the button calls the wizard to create a new project. After its appearance, click the Next button (Fig. 3).

Enter the name of the project, in the Project Name field we write “eco_flow”. Specify where the project will be located: in the Project location field specify the directory with the project. I will have it “F: / Projects / FPGA-Systems / eco_flow / projects / vivado”. If you check the “create project subdirectory” checkbox, an additional folder with the project name will be created. Click Next (fig. 4).

Figure 4 - Entering the name of the project and its location

We create an ordinary project, so we simply select the type of project RTL. At the current stage, we will not add any files to the project, so we’ll check the box “Do not specify sources at this time” and click Next (Fig. 5).

Figure 5 - Selecting the type of project being created

We will work with the Arty board [2], so we will choose the crystal that is installed on it: xc7a35tcsg324-1. Click Next (fig. 6).
Note: I do not specifically choose a ready board from a template of available boards. This is done so that you can manually make mistakes, which we will fix later.

Figure 6 - Crystal Selection xc7a35tcsg324-1

The final in the New Project Setup Wizard will be the Summary window of the project being created. Click Finish (Fig. 7).

Figure 7 - The brief information window of the project being created

3.2. Creating and adding HDL files to the project

Here we will create two modules: just a flashing LED and a block memory, which is constantly read (in fact, this is an imitation of the memory of filter coefficients, the values ​​of which we later try to change).

To create and add a new file to the project, use the wizard, which is called by pressing the blue plus (Fig. 8).

Select Create file, then in the window that appears in the File name field, enter the name of the flash_led file to be created, click OK (Fig. 10).

Figure 10 - Creating a new file and entering its name

After that, the file will appear in the list of entries. Click Finish (Fig. 11)

Figure 11 - List of added or created files

Now the wizard to create a template for the file. Since I use VHDL, I can change the architecture name to rtl. We create two pins of our module: iclk with the “in” direction (clock signal of our module) and oled with the “out” direction (output connected to the LED). Click OK (Fig. 12).

Now our module is in the project tree (Fig. 13).

Figure 13 - The created flash_led module

The module should perform a simple function: just blink the LED with a period of 1 second. Looking ahead, I will say that the clock frequency of our project will be equal to 100 MHz, and the module itself will still be useful for you when doing homework.
Replace the contents of the file with the following (Listing 1 (text version of listing 1 see Appendix A)). The code is quite simple, and does not require additional comments to explain its work.

Now create a new module, which should be called brom_reader, its iclk ports with the “in” direction, and odout [7: 0] with the “out” direction (repeat the steps from Fig. 8 to Fig. 12).
If everything is done correctly, then the brom_reader module should appear in the project tree (Fig. 14).

Replace the contents of the module with the following text (Listing 2 (text version of Listing 2, see Appendix B)). Here you will need a few comments:

1. Line 13: type alias is created for std_logic_vector. Those who work with VHDL often use the data type "std_logic_vector ()". In order not to write these long names each time, you can declare an alias and then use it throughout the module code.
2. Lines 14–20: standard declaration of a two-dimensional array of natural numbers and array initialization (memory is created with numbers).
3. Line 22: use of the alias slv to declare a signal
4. Lines 23-24: use of the synthesis attribute [11]. Why is he registered here? We have created a rather small two-dimensional array (lines 15-20) - and, most likely, during the synthesis it will be optimized and implemented as distributed memory on the LUT. And since we want to place the array in the block memory (BRAM-Block RAM), we need to explicitly tell the synthesizer about this, which is done with the help of synthesis attributes. Read more about them in the Vivado synthesis manual in [11].

Otherwise, everything should be clear: we created a ROM-memory from which its contents are continuously, sequentially and cyclically read.

3.3. Creating a MicroBlaze project and working in IP Integrator

Now we will create a project with MicroBlaze. Once again, I would like to draw your attention to the fact that there is a step-by-step guide in Russian on creating projects on the MicroBlaze software processor for beginners [16].
To create a block project, you must create a Block Design. Select Create Block Design, enter the name system and click OK (Fig. 15).

After adding MicroBlaze to the working field, we will use the express settings of the soft processor. Select Run Block Automation and set the settings in accordance with Fig. 17. Click OK.

Figure 17 - MicroBlaze Express Setup

Perform configuration of some modules in accordance with our Arty board. Configure the clock grid generation module clk_wiz_1. To call the module settings, double-click it with the left mouse button. In the settings window, set the value of the input clock frequency of 100 MHz, since it is the generator at 100 MHz that is installed on the board [12]. We also set the type of source as unipolar (Fig. 19). Go to the Output Clocks tab, where we configure the output frequency of the module.

Figure 20 - Setting the parameters of the output frequency

Scroll down to configure additional overhead. We will remove the reset reset signal, which we will not use. Uncheck it (fig. 21). The rest of the settings we do not need, click OK.

Now we declare the clk_in1 input of the clk_wiz_1 module external, in fact we make from it the input of our Block Design. To do this, click on clk_in1 with the right mouse button and select Make External (Fig. 22).

Figure 22 - Making the port clk_in1 external

As you can see port clk_in1_0 appeared (Fig. 23).

Figure 23 - Input port clk_in1_0

In the reset control module of our processor system, we connect two unused inputs (external reset and additional reset) to the inactive logic level "1". We do this with an IP block called constant. To do this, click the blue cross at the top, then in the search bar enter “const” "and select the module constant.

Perform the configuration of the xlconstant_0 module by double-clicking on it with the left mouse button. In the line value (Const val) enter 1, in the line width (Const Width) enter 1, press OK (Fig. 25)

Let us connect the dout output of the xlconstant_0 module to the ext_reset_in and aux_reset_in inputs of the rst_clk_wiz_1_100M module. Just connect these ports with the mouse (Fig. 26).

Perform the configuration of the axi_uartlite_0 module, setting the transmission settings in accordance with Fig. 28. Then click OK.

axi_uartlite_0 . . Run Connection Automation (AXI UART AXI MicroBlaze) . 29.

UART Vivado IP Integrator. 2 . 29 , rx tx axi_uartlite_0 . , . , , , HDL , , (rx tx).
Regenerate Layout. Block Design , . 30. , . , , , .

Configure the module in accordance with Fig. 32 (we will use only one channel and one output).

Let us connect the axi_gpio_0 module to the processor and make the output external. Click Run Connection Automation and check all the checkboxes (Fig.33).

Click the Regenerate Layout button and make sure all connections match pic. 34

HDL Insertion Flow, HDL . , . Netlist Insertion Flow.
AXI , ILA AXI ( Monitor Type ILA). , SLOT_0_AXI ila_0 AXI, . , axi_uart_0 (. 36). clk Regenerate Layout.

1024, .
RTL Block Design, flash_led, Add Module to Block Design ( Vivado 2017.1).

iclk flash_led_0 , oled ( , Make Exernal). Regenerate Layout.

, . 38.

, brom_reader. iclk , odout[7:0] . Regenerate Layout. , . 39.

, ILA odout[7:0] brom_reader_0.
IP ILA (. 35) Diagram. , . Monitor Type Native ( AXI, ). . Probe_Ports(0..7) . 40.

Connect the odout [7: 0] output of the brom_reader_0 module to the probe_0 [7: 0] input of the ila_1 module, and connect the clk input of the ila_1 module to the clock circuit of our project. Click the Regenerate Layout button, and if everything is correct, it should turn out as in fig. 42

It remains only to add the button and the LED directly connected to it.
Create an input port by clicking on an empty space of our block diagram with the right mouse button and selecting Create Port (Fig. 43).

Figure 43 - Creating a port in IP Integrator

, ibtn, input , . OK (. 44).

Diagram (. 45).

45 – ibtn

obtn_led, output ( . 43-44).
ibtn c obtn_led, Regenerate Layout. . 47.

, Block Design, Validate Design. , Vivado . OK Block Design (. 48).

3.4.

Figure 48 - Creating a project wrapper

After that, Vivado will offer to manually update the HDL wrapper when you make changes to Block Design, or to do it automatically. We leave the automatic update and click OK (Fig. 49).

Figure 49 - HDL Wrap Upgrade Options

Figure 50 - Making the system_wrapper module a top module

Now let's perform the synthesis of the system_wrapper module by clicking on the Run Synthesis button (Fig. 51).

Figure 51 - Starting the synthesis of the project

After clicking on the Run Synthesis button, click OK and wait until the synthesis is complete.

Figure 52 - Opening the results of the synthesis

Figure 53 - Opening the window for pin assignment

Using the Reference Manual [12] for Arty, assign the legs (Fig. 54).

Figure 54 - Assignment of project legs (rx and tx UART are confused specially)

Click the save button, after which Vivado will indicate that you did not create the design constraints file, and will offer to create it. Enter the file name constr and click OK (Fig. 55).

Figure 55 - Creating a design constraint file

. Generate Bistream, OK (. 56).

56 – Generate Bitstream

Bitstream . Cancel (. 57)

57 –

3.5. MicroBlaze

MicroBlaze. Xilinx Software Development Kit (SDK). SDK (IP , AXI) SDK. File → Export → Export Hardware (. 58).

58 – SDK

Figure 59 - Export Parameters Window

Now run the SDK. To do this, select File → Launch SDK

Figure 60 - Launch the SDK

Figure 61 - Creating a new project in the SDK

Enter the name of the new MB_run project, click Next (fig. 62)

Figure 62 - Setting up a new project

Figure 63 - Selecting a template for the project being created

Figure 64 - Location of the helloworld.c file Listing 3 - Replaced contents of the helloworld.c file

3.6. Running the program and debugging

After writing the code and assembling the processor system, you need to make sure that:

1. LD4 LED is lit by pressing the BTN0 button
2. The processor works and sends “Hello World: cycle” to the console, however, we don’t see the words in the console, because we made the wrong connection rx and tx. An additional signaling device of the processor is the flashing LED LD1.
3. AXI-Lite transactions from the processor to the UART are executed.
4. The block memory is read and gives the correct values.

First we connect Arty to the computer. Perform the setting of the terminal in which the UART messages should be displayed. This can be done using standard SDK tools. The SDK has a terminal located below (Fig. 65).
If there is no terminal, then it can be found in Window → Show View → Others → Xilinx → SDK Terminal (Fig. 65).

Set the terminal settings, in accordance with Fig. 66. COM port number may vary.

Now let's go to Vivado and execute FPGA programming.

Figure 67 - Opening the Hardware Manager and connecting to the FPGA

(. 68)

68 –

, .bit .ltx (.69) Program.

, LD4 , BTN0 LD4.
UART LD1.
SDK, MB_run, Run As → Launch on Hardware (System Debugger), . 70. , .

, , LD1 , SDK Terminal , rx tx .
, , UART - .
Vivado. , , ILA: AXI UART, . ILA (. 71).

71 – ILA

, , , , . , , UART - . «», , , , ILA.
hw_ila_1 .
Trigger Setup , . , . 72. OK.

: AXI-Lite, . , . , , [14].

. RVALID «1», , , «1». , . 73. .

, , , . . 74

74 – AXI-Lite

Change the displayed bus status to ASCII. To do this, right-click on the bus, then select Radix, then ASCII (Fig. 76).

After that we will see on the bus a part of our message that the processor sends out. This partially confirms that the transaction is correct (Fig. 76).

Try repeating the actions from fig.71 to fig. 76 for hw_ila_2, which is connected to the output of the block memory reader module. Install the trigger is not required. If everything is done correctly, the picture should be similar to fig. 77.

This completes the test project build, and we can start editing our netlist and working in ECO mode.

4. ECO

:

1. BTN0
2. UART , ( rx tx)
3. ( ASCII:”author: KeisN13”).

, ECO, Design Checkpoint (DCP). DCP, (post route).
Vivado DCP, DCP «» DCP .
edited_dcp. (. 78)

DCP , «_/_.runs/_/___routed.dcp» (. 79) edited_dcp.

Go to Vivado and perform the opening of the DCP. To do this, click File → Open Checkpoint (Fig. 80)

Select the location of the copied DCP file in the edited_dcp folder and click OK.

There are several modes of operation with DCP, but today we are interested in ECO Flow. To switch to ECO mode, you must change the view. To do this, select ECO in the upper right corner of the drop-down list (Fig. 82).

Figure 82 - Transition to ECO mode

, ECO (. 83). , .

5. ECO:

ECO , . 84. DCP. DCP , / Tcl-. , , , . , (, .bit) (.ltx). « », , . – DCP .

. [3] Vivado ECO Flow.
ECO , , .
ECO Navigator, . ECO Navigator .
Edit (. 85): ,

Create Net: , . , . . pin port, , Connect selected pins and ports (. 86).

Create Cell: , . . , , black box. LUT, , (. 87).

87 – Create Cell

Create Port: . : , , .. (. 88).

88 – Create Port

Create pin: . ( cell) . create_port. , (. 89).

Connect Net: . . , .
Disconnect Net: , . , cell, , .
Replace Debug Probes: , ILA / VIO (Virtual Input Output), , .
Place Cell: cell .
Unplace Cell: cell .

Run
Run , .

Scratch
, , , . Con , PnR .
Scratch (. 90). , , . , [3] Vivado ECO Flow → Scratch Pad → Scratch Pad Pop-up Menu.

6.

. , , . , LD0 , BTN0 . , , .

6.1.

, ibtn, , F4. , , .

, ibtn. ibtn LD1 ( obtn_led). ibtn, Expand Cone To Flops or I/Os. Regenerate Layout (. 92)

«» (. 93).

, , , . system_i . obtn_led system_i I obtn_led_OBUF_inst, Edit Disconnect Net.

Regenerate Layout , (. 95)

Scratch Pad, .
. Edit Create Cell, invertor, INV OK (. 96)

INV (. 97)

, LUT. , LUT , , , Cell Properties, Truth Table Edit LUT Equation… (. 98).

. , Scratch Pad I0 invertor obtn_led system_i.

. Edit Create Net. btn_led, (. 100)

. Regenerate Layout (. 101)

O invertor I obtn_led_OBUF_inst. -, . btn_led_o. . 102

102 –

DCP , (. 103).

Due to the fact that we did not perform the placement and tracing, a series of errors will appear that speak of this.

Now we will try to generate a bit firmware file, and see if it worked out to make changes correctly. To do this, you must consistently perform the steps from the section Run, not all of course and without any options. Everything remains by default (fig. 104).

Click Place Design and without entering any options click OK. After waiting for the completion of operations, click Route Design and select Incremental Route in the window that appears, click OK.

After that, we generate a bit file by clicking on Generate Bitstream. Make sure that the edited_dcp folder is in the file path field. After that, open the Hardware Manager for the firmware of our FPGA.

, Vivado. , Vivado Hardware Manager (. 105). , .bit ILA .ltx

105 – Hardware Manager Vivado

, .67-69 . , , edited_dcp (. 106).

106 –

, LD0 , BTN0 .

6.2. /

ECO . brom_reader, , , . BROM INIT, .
Netlist brom_reader (.107).

, , Cell Properties (. 108). Properties INIT.

You can change the property of a component by clicking on the pencil icon and entering new values ​​or using the Tcl console and the set_ptoperty command.
Replace the property values ​​according to Fig. 110 and save the result:

INIT_00: 256'h0061006700700066002E00770077007700200020002000200020002000200020

INIT_01: 256'h0020002000200020002000750072002E0073006D00650074007300790073002D

, . Generate Bitstream . .ltx, (. 111).

Hardware manager FPGA .bit .ltx (.112). , edit_dcp.

, . 73-75 ( hw_ila_2, ASCII ). , . 113.

, , , , . , , , , MMCM PLL . , , , , (Report Timing Summary ..).

6.3. ILA

, ECO , . , , « ». , gnd vcc.

, , , .

ECO, , ; .

: , « », : . : , , Disconnect Net . «DONT_TOUCH» ( «unrote») – Disconnect Net . .

, , . , brom_reader. . , (. 114). cnt, , 5.

114 –

Replace Debug Probes. 31, 5 , ila_1, Edit Probes (. 115). ila, . , .

, *cnt[*]. , . , 5 , 5 . contains match tcl . Tcl , .

«0», Vivado , gnd const0. , Edit Probes (.117).

*const0 , , (. 118). !!! Debug Hub (dbg_hub), Vivado , . IP, , uartlite.

ila_1 . 119. , . , DRC.

OK , , DONT_TOUCH , ila_1. , . , , . , Unset Property DCP.
, , (.120). 1 . , !

120 –

Hardware Manger , .bit .ltx .
hw_ila_2 4 : cnt const0. cnt hex unsigned decimal ( . 75) , . , cnt 0 31 1 (.121).

, .

6.4. /

, rx tx uart - Hello World . , ECO , . .

. , , cell, . , .

.

uart_rtl_0_rxd, . unplace cell (. 122). , , .

. uart_rx, Create Port . 123

A9 , Vivado , A9. (. 124)

. Create Cell, ibuf_rx (. 125)

125 –

. . , . uart_rx Create Net. rx_net.

I Connect Net. (. 127)

, system_i. O uart_rtl_0_rxd, system_i Create Net

.
uart_rtl_0_txd, . Unplace cell, , (. 122). , , .

uart_tx, Create Port, Output LVCMOS33 (. 130)

130 –

tx_net, uart_tx. uart_tx Create Net

tx_obuf, Create Cell OBUF (. 132)

O , uart_tx Connect Net.

system_i. I uart_rtl_0_txd (. 134).

. (. 135).

Hardware Manager . SDK (. . 70). , Hello World: cycle (. 136).

7.

, . , , , .. , , .. HDL , , «-» . 1. , , . , . , IP Integrator – IP RTL.

Table 1. Comparative analysis of the time spent on obtaining the final firmware file in various modes.

8. Conclusion

Have I ever applied the ECO mode in practice? Yes. , , , . ECO; , Tcl-, . , ECO – , LogicAnalyser (ChipScope) ILA ( ) . , , - , .
ECO Flow , , : Vivado ECO Flow.
. Good luck!

9.

1. , LUT, , .
2. ECO. Tcl Vivado [9].
3. AXI-lIte, GPIO. ECO , ila_1 uartlite, gpio.
4. * , MMCM, 100. 50 . , . , , .
5. * Tcl , ECO. , , , ..
6. ** , brom_reader, 32 ASCII, /

1. Vivado Xilinx
2. Arty Board Digilent
3. UG904 Vivado Design Suite User Guide: Implementation
4. UG908 Vivado Design Suite User Guide Programming and Debugging
5. UG986 Vivado Design Suite Tutorial: Implementation
6. Wiki : ECO
7. UG949 UltraFast Design Methodology Guide
8. UG892 Vivado Design Suite User Guide Design Flows Overview
9. UG835 Vivado Design Suite Tcl Command Reference Guide
10. UG894 Using Tcl Scripting
11. UG901 Vivado Design Suite User Guide Synthesis
12. Arty Reference Manual
13. UG908 Programming and Debugging
14. UG1037 Vivado Design Suite AXI Reference Guide
15. Hex-to-ASCII
16. Lead: Developing a MicroBlaze software processor Xilinx Vivado IDE / HLx Environment

 library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity flash_led is Port ( iclk : in STD_LOGIC; oled : out STD_LOGIC); end flash_led; architecture rtl of flash_led is signal cnt : natural range 0 to 100_000_001 := 0; signal led : std_logic := '0'; begin process(iclk) begin if rising_edge(iclk) then if cnt = 100_000_000 then cnt <= 0; else cnt <= cnt + 1; end if; if cnt < 50_000_000 then led <= '0'; else led <= '1'; end if; end if; end process; oled <= led; end rtl; 

 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity brom_reader is Port ( iclk : in STD_LOGIC; odout : out std_logic_vector(7 downto 0) ); end brom_reader; architecture rtl of brom_reader is alias slv is std_logic_vector; type rom_type is array (0 to 31) of natural; signal rom : rom_type := ( 32 , 32, 32, 32, 97, 117, 116, 104, 111, 114, 58, 32, 75, 101, 105, 115, 78 , 49, 51, 32, 32, 32, 32, 32, 32 , 32, 32, 32, 32, 32, 32, 32 ); signal cnt : natural range 0 to rom'length-1 := 0; signal dout: slv(odout'range) := (others => '0'); attribute RAM_STYLE : string; attribute RAM_STYLE of rom : signal is "BLOCK"; begin process(iclk) begin if rising_edge(iclk) then dout <= slv(to_unsigned(rom(cnt), dout'length)); if cnt = (rom'length - 1) then cnt <= 0; else cnt <= cnt + 1; end if; end if; end process; odout <= dout; end rtl; 

 #include "platform.h" #include "xil_printf.h" #include "xparameters.h" #include "xgpio.h" XGpio Gpio; /* The Instance of the GPIO Driver */ #define DELAY 10000000 int main() { init_platform(); int Status; volatile int Delay; int k = 0; /* Initialize the GPIO driver */ Status = XGpio_Initialize(&Gpio, XPAR_GPIO_0_BASEADDR); if (Status != XST_SUCCESS) { xil_printf("Gpio Initialization Failed\r\n"); return XST_FAILURE; } /* Loop forever blinking the LED */ while (1) { /* Set the LED to High */ XGpio_DiscreteWrite(&Gpio, 1, 1); xil_printf("Hello World: cycle %d\n\r", k); k++; /* Wait a small amount of time so the LED is visible */ for (Delay = 0; Delay < DELAY; Delay++){}; /* Clear the LED bit */ XGpio_DiscreteWrite(&Gpio, 1, 0); /* Wait a small amount of time so the LED is visible */ for (Delay = 0; Delay < DELAY; Delay++){}; } cleanup_platform(); return 0; } 

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