Examination of internal FPGA defects: we are looking for a black cat in a dark room

Season 1. The project on Virtex5 does not work, although on the other batch of crystals everything is in order.



Once it happened that the board with the XC5VSX95T crystal did not work. It was known that this is a new batch of crystals. To test the problem, a test was written to test all FPGA slices in a row. Testing of the crystals showed the presence of faulty LUT modules, which are 4 elements each in one slice. It turned out that the triggers in these slices are in order, and then a memory block was created on the triggers, which in turn were created on the LUT. See fig. 1. Here is an example of a trigger on LUT4. Each cell (bit) in the test is responsible for one slice. The trigger cell uses all four LUT slices. The crystal was divided into 5 areas (and in the other test 9 areas), which were tested separately, each with its own firmware. Proper placement of used slices was regulated by LOC attributes. Fault is characterized by the inability to change the state of the tested trigger. The output of such a trigger can be read 0 or 1, but always the same. Therefore, at first the memory was filled with 1, and checked, then 0, and checked. The full range of slices is: X0Y0 - X91Y159. (14,720 slices)





Pic1



Figure 2 illustrates the structure of the Virtex5 PLIS slice and indicates the faulty components. It was LUT5 that turned out to be faulty. The full code of the project for the known reasons is not placed. However, in the archive you can find the VHDL implementation code of the memory cells on the triggers and on the LUT.

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Pic2



Testing 3 boards showed:



BOARD # 2 18 BAD SLICES:

SLICE_X26Y120 - SLICE_X26 Y128

SLICE_X27Y120 - SLICE_X27 Y128



BOARD # 3 19 BAD SLICES:

SLICE_X26Y120 - SLICE_X26 Y128

SLICE_X27Y120 - SLICE_X27 Y128

SLICE_X26Y129



BOARD # 4 19 BAD SLICES:

SLICE_X26Y120 - SLICE_X26 Y128

SLICE_X27Y120 - SLICE_X27 Y128

SLICE_X26Y131



Conclusion:

when using boards, it is required to exclude bad slices from the development by the command

CONFIG PROHIBIT = SLICE_X26Y120: SLICE_X27Y128;

CONFIG PROHIBIT = SLICE_X26Y129;

CONFIG PROHIBIT = SLICE_X26Y131;



Or it is better to exclude immediately all possible with a margin:

CONFIG PROHIBIT = SLICE_X26Y120: SLICE_X27Y131;



With a shortage of resources, it is possible to organize a simulation of the use of defective LUTs, in order to be able to use the remaining operational elements of these slices.