Asynchronous decoder

As promised in the previous article, this article will focus on the representation of operations on addresses in an asynchronous form. As an example, I will describe the address decryption operation. Immediately I want to prevent the insinuations that I encountered after the publication of the previous article. It's about a fully and asynchronous device. And please do not refer to the abstract of the Uzbek University. Supposedly an asynchronous decoder can be obtained from synchronous using simple manipulations. At the same time a question to those who claim that the asynchronous processor was made 20 years ago. How did you manage this without an asynchronous decoder?

So, about the asynchronous descrambler. After reflection, I came to the conclusion that the only sane way for the synthesis of an asynchronous decoder is a phased doubling of the address using the add-on scheme over two decoders that is half the size of the address. Prove that there is no alternative way, I do not undertake. But I can say that the alternative path (if there is one) is much more expensive in terms of the number of added new signals.

In view of the foregoing, the discussion in this article will deal with a two-digit decoder. How to double the width of an asynchronous decoder, the topic of the next article.
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So, we will describe the initial behavior of a two-bit asynchronous decoder. Oddly enough, it is not difficult to do in the language of STG, and the point here is not even a small bit.

Input Signals:
d - signal - command for address decryption operation;
r1, r2 - signals of bits of the register of the address.

Output signals:
q1 - switches if r1 = 1 and r2 = 1;
q2 - switches if r1 = 1 and r2 = 0;
q3 - switches if r1 = 0 and r2 = 1;
q4 - switches if r1 = 0 and r2 = 0.

The stepwise execution of the decryption operation is as follows:
0. When the signal d is 0, the external control circuit (MSC) randomly switches the signals r1 and r2. The decoder circuit (SD) does not track changes in the signals r1 and r2.
1. The MAS produces a d + signal, a command for the decryption operation. At this point, the MAS sets the signals r1 and r2 to a specific value. The MAS ensures that until the end of the decryption operation, the signals r1 and r2 will not change their value.
2. Depending on the value of the signals r1 and r2, the LED produces one of the signals: either q1 +, or q2 +, or q3 +, or q4 +.
3. The MAS produces a d- signal.
4. The LED produces one of the signals in accordance with clause 2: either q1-, or q2-, or q3-, or q4-. This signal is the signal for the end of the decryption operation. After that, the MAS can again change the signals r1 and r2 in an arbitrary manner.

A bit of discussion about how the two-bit asynchronous decoder circuit was synthesized. In fact, it consists of two, occurring in parallel, “level choices” (for each of the signals r1 and r2). Read more about the “level selection” here. Then alternative branches in two parallel processes are synchronized in pairs. The result is four alternative branches. In the above graph of the adjusted final behavior, only four alternative branches are visible. But this is a tribute to the STG language. It is not convenient to describe on it actually occurring processes. All the above “choices by level” and “synchronization of alternative branches” are encrypted in this behavior.

You can add that the synthesized behavior is not the result of some insights. This is the result of a targeted application of the methodology presented here. For each new signal, there is a rationale for adding it.

As a result, according to the presented graph of the final behavior, you can obtain logical functions for each signal:

e = N O T (o 1)

$e = NOT (o1)$ ;

e 1 = A N D (o 1, j 1)

$e1 = AND (o1, j1)$ ;

e 2 = A N D (o 2, h 1)

$e2 = AND (o2, h1)$ ;

e 3 = N A N D (e, i 1)

$e3 = NAND (e, i1)$ ;

e 4 = O R (o 2, h 1)

$e4 = OR (o2, h1)$ ;

f 1 = A N D (d, r 1)

$f1 = AND (d, r1)$ ;

f 2 = A N D (d, r 2)

$f2 = AND (d, r2)$ ;

g = N O T (d)

$g = NOT (d)$ ;

h 1 = N O R (g, r 1)

$h1 = NOR (g, r1)$ ;

h 2 = N O R (g, r 2)

$h2 = NOR (g, r2)$ ;

i 1 = N O R (f 1, j 1)

$i1 = NOR (f1, j1)$ ;

i 2 = N O R (f 2, j 2)

$i2 = NOR (f2, j2)$ ;

j 1 = N O R (g, i 1)

$j1 = NOR (g, i1)$ ;

j 2 = N O R (g, i 2)

$j2 = NOR (g, i2)$ ;

k 1 = A N D (e 1, j 2)

$k1 = AND (e1, j2)$ ;

k 2 = A N D (e 1, h 2)

$k2 = AND (e1, h2)$ ;

k 3 = A N D (e 2, j 2)

$k3 = AND (e2, j2)$ ;

k 4 = A N D (e 2, h 2)

$k4 = AND (e2, h2)$ ;

l 1 = A N D (t 1, i 2)

$l1 = AND (t1, i2)$ ;

l 2 = N O R (t 2, h 2)

$l2 = NOR (t2, h2)$ ;

l 3 = A N D (t 3, i 2)

$l3 = AND (t3, i2)$ ;

l 4 = N O R (t 4, h 2)

$l4 = NOR (t4, h2)$ ;

m 1 = N O R (k 1, n 1)

$m1 = NOR (k1, n1)$ ;

m 2 = N O R (k 2, n 2)

$m2 = NOR (k2, n2)$ ;

m 3 = N O R (k 3, n 3)

$m3 = NOR (k3, n3)$ ;

m 4 = N O R (k 4, n 4)

$m4 = NOR (k4, n4)$ ;

n 1 = N O R (l 1, m 1)

$n1 = NOR (l1, m1)$ ;

n 2 = N O R (l 2, m 2)

$n2 = NOR (l2, m2)$ ;

n 3 = N O R (l 3, m 3)

$n3 = NOR (l3, m3)$ ;

n 4 = N O R (l 4, m 4)

$n4 = NOR (l4, m4)$ ;

o 1 = N O R (p 1, p 2)

$o1 = NOR (p1, p2)$ ;

o 2 = N O R (p 3, p 4)

$o2 = NOR (p3, p4)$ ;

p 1 = N O R (m 1, s 1)

$p1 = NOR (m1, s1)$ ;

p 2 = N O R (m 2, s 2)

$p2 = NOR (m2, s2)$ ;

p 3 = N O R (m 3, s 3)

$p3 = NOR (m3, s3)$ ;

p 4 = N O R (m 4, s 4)

$p4 = NOR (m4, s4)$ ;

s 1 = N O R (n 1, l 1)

$s1 = NOR (n1, l1)$ ;

s 2 = N O R (n 2, l 2)

$s2 = NOR (n2, l2)$ ;

s 3 = N O R (n 3, l 3)

$s3 = NOR (n3, l3)$ ;

s 4 = N O R (n 4, l 4)

$s4 = NOR (n4, l4)$ ;

t 1 = N O R (e 3, s 1)

$t1 = NOR (e3, s1)$ ;

t 2 = O R (e 3, s 2)

$t2 = OR (e3, s2)$ ;

t 3 ​ ​ = N O R (e 4, s 3)

$t3 = NOR (e4, s3)$ ;

t 4 = O R (e 4, s 4)

$t4 = OR (e4, s4)$ ;

q 1 = N O R (s 1, k 1)

$q1 = NOR (s1, k1)$ ;

q 2 = N O R (s 2, k 2)

$q2 = NOR (s2, k2)$ ;

q 3 = N O R (s 3, k 3)

$q3 = NOR (s3, k3)$ ;

q 4 = N O R (s 4, k 4)

$q4 = NOR (s4, k4)$ .

As you can see, all the equations are placed in the basis of 2-NOT, 2-OR-NOT.

But actually the SI itself is a two-bit asynchronous decoder circuit.

I do not have the opportunity to test the circuit in real embodiment. But if someone is interested in this, I will only welcome it. To make the initial setting, the input signal d must be set to 0. The internal signals m1, m2, m3, m4 must be set to 1. In order not to leave the two-input basis, this can be done for each of the elements m1, m2, m3, m4 as follows .

The element on the left is converted to the subschema on the right. The input signals r1, r2 can be set arbitrarily.

Source: https://habr.com/ru/post/335178/

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Asynchronous decoder

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