Current activity around MIPSfpga and not only

There are several events and topics that I would like to share with the community. In an amicable way, you can write a separate article for each one, but the general lack of time makes it a bit tricky. Our current topics:

• MIPSfpga 2.0 release;
• processor schoolMIPS and Summer School for Young Programmers in Novosibirsk;
• School-seminar on digital design and computer architecture in Tomsk;
• Launch of the vanilla Linux kernel on MIPSfpga-plus;
• support for Altera MAX10 ADC in MIPSfpga-plus;
• logo MIPSfpga-plus.

If you are not indifferent to the MIPSfpga-plus topic, then at the end there is a small survey on what I should write (or not write) the following article. Your choice will help me navigate and prioritize. Welcome !

MIPSfpga 2.0 release

Two years after the first release of MIPSfpga, Imagination Technologies released the second version of the package: MIPSfpga 2.0 [ L1 ].

What you should pay attention to:

• As before, MIPSfpga is presented not only as the source code of an industrial processor core under an academic license, but also as a set of educational materials, which also includes documentation and laboratory work. And this is wonderful, because the book “Digital circuit design and computer architecture” (H & H) [ L2 ], which was recently translated into Russian, gives us a very high-quality and accessible set of theory and practice presented on the example of the MIPS architecture;
• At the recently held Toronto Symposium [ L3 ], Sarah Harris (one of the H & H authors) presented a collective article [ L14 ], which provides a detailed description of MIPSfpga 2.0, as well as an analysis of the spread of the educational initiative of Imagination Technologies for universities. And (wow!) My name is even mentioned there because of the activity in the MIPSfpga-plus project.
• if the first release was mainly focused on how to assemble a system on a chip (SoC) based on MIPSfpga, then the second focus is shifted to the work of the processor itself:

• the kernel itself, according to preliminary information, has not undergone any special changes, it is all the same MIPS microAptiv UP, on the basis of which, for example, Microchip PIC32MZ is built;
• orientation to Xilinx remained unchanged when building SoC in laboratory work. So, the general scheme used in the laboratory work of SoC is as follows, which somewhat limits the launch on Altera-based boards:
  
  

If we take into account that the company Digilent artificially restricts the supply of its motherboards for Xilinx without FPGA to Russia and Ukraine, the picture is not very pleasant. But here we are come to the rescue by MIPSfpga-plus - opensource project for building SoC based on MIPSfpga with platform-independent peripherals [ L4 ]. For correct interaction with MIPSfpga 2.0 it may have to be slightly modified.

schoolMIPS and Summer School for Young Programmers

The Summer School for Young Programmers has opened in Novosibirsk today [ L5 ]. The school curriculum involves the division into workshops [ L6 ], one of which is focused on teaching Verilog and microchip architecture. The guys will be a teacher , Yuri Panchul YuriPanchul , who specifically flew from the States for this business.

This is cool, and I, frankly, I envy these schoolchildren a little - in my childhood this was not the case.

Especially for this event, we wrote a small processor MIPS-architecture: schoolMIPS [ L7 ], which is planned to be used in the educational process. It is built by simplifying the Sarah Harris processor, described in H & H [ L2 ]. Key Features:

• Verilog hardware description language;
• a subset of the MIPS architecture with instruction memory, with general-purpose registers, but without data memory;
• single cycle microarchitecture;
• minimum set of instructions, initially sufficient to calculate the Fibonacci number and integer square root in an iterative way;
• Simplified for teaching microarchitecture and code;
• compilation of programs carried out by the MIPS toolchain.

Included is a small instruction and slides describing the construction of the processor core in the style similar to H & H [ L2 ].

In addition to writing the processor, a fairly large-scale translation into Russian of various educational materials was made. I will not touch on this topic, because I did not participate, I believe that Yuri YuriPanchul will write more about this in the future.

School-workshop on digital design and computer architecture in Tomsk

From September 18 to September 22, a School-Workshop on digital design and computer architecture in the era of systems on a chip (SoC) and Internet technologies (IoT) will take place on the basis of Tomsk State University. The preliminary school program and the list of participants are published on the website [ L8 ]. Your humble servant will also perform there: I plan to tell you about AHB-Lite, connect peripherals to MIPSfpga, work with SDRAM is from the stage. And informally we can discuss Linux, connecting the debugger and any code I brought to MIPSfpga-plus. Come!

Running Linux on MIPSfpga-plus

Laboratory work MIPSfpga describes the launch of Linux on the SoC, built using Xilinx-specific peripheral modules. Coupled with the problem already mentioned above with access to the boards, this created some difficulties. The necessary minimum for running Linux are: MMU (available as part of MIPS fpga), sufficient memory and UART. At the same time, most of the work on porting the system has already been done by Imagination Technologies, the corresponding code is included in the main branch of the kernel [ L9 ]. Just a week ago, I managed to run Linux on Terasic DE10-Lite and I wouldn’t say that the patch needed for this was very difficult.

Key Features:

• system configuration: FPGA Altera MAX10, SDRAM 64Mb, MIPSfpga-plus, UART16550;
• The kernel is loaded into memory with EJTAG [ L10 ];
• mmc / sdcard is not yet supported, so it’s not possible to talk about booting from a memory card. On the other hand, in MIPSfpga labs, booting from a flash drive is also not a question.

Linux version 4.12.2+ (stas@ubuntu) (gcc version 4.9.2 (Codescape GNU Tools 2016.05-03 for MIPS MTI Linux) ) #67 Wed Jul 19 00:07:19 MSK 2017 CPU0 revision is: 00019e60 (MIPS M14KEc) MIPS: machine is terasic,de10lite Determined physical RAM map: memory: 04000000 @ 00000000 (usable) Initrd not found or empty - disabling initrd Primary instruction cache 4kB, VIPT, 2-way, linesize 16 bytes. Primary data cache 4kB, 2-way, VIPT, no aliases, linesize 16 bytes Zone ranges: Normal [mem 0x0000000000000000-0x0000000003ffffff] Movable zone start for each node Early memory node ranges node 0: [mem 0x0000000000000000-0x0000000003ffffff] Initmem setup node 0 [mem 0x0000000000000000-0x0000000003ffffff] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 16256 Kernel command line: console=ttyS0,115200 PID hash table entries: 256 (order: -2, 1024 bytes) Dentry cache hash table entries: 8192 (order: 3, 32768 bytes) Inode-cache hash table entries: 4096 (order: 2, 16384 bytes) Memory: 60512K/65536K available (1827K kernel code, 97K rwdata, 320K rodata, 948K init, 184K bss, 5024K reserved , 0K cma-reserved) NR_IRQS:8 clocksource: MIPS: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 38225208935 ns sched_clock: 32 bits at 50MHz, resolution 20ns, wraps every 42949672950ns Console: colour dummy device 80x25 Calibrating delay loop... 10.81 BogoMIPS (lpj=21632) pid_max: default: 32768 minimum: 301 Mount-cache hash table entries: 1024 (order: 0, 4096 bytes) Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes) devtmpfs: initialized clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns futex hash table entries: 256 (order: -1, 3072 bytes) clocksource: Switched to clocksource MIPS random: fast init done workingset: timestamp_bits=30 max_order=14 bucket_order=0 Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled console [ttyS0] disabled b0400000.serial: ttyS0 at MMIO 0xb0401000 (irq = 0, base_baud = 3125000) is a 16550A console [ttyS0] enabled Freeing unused kernel memory: 948K This architecture does not have kernel memory protection. mount: mounting devpts on /dev/pts failed: No such device mount: mounting tmpfs on /dev/shm failed: Invalid argument mount: mounting tmpfs on /tmp failed: Invalid argument mount: mounting tmpfs on /run failed: Invalid argument Starting logging: OK Initializing random number generator... done. Starting network: ip: socket: Function not implemented ip: socket: Function not implemented FAIL Welcome to MIPSfpga mipsfpga login: root Jan 1 00:00:09 login[43]: root login on 'console' # uname -a Linux mipsfpga 4.12.2+ #67 Wed Jul 19 00:07:19 MSK 2017 mips GNU/Linux # free -m total used free shared buffers cached Mem: 60 3 56 0 0 2 -/+ buffers/cache: 0 59 Swap: 0 0 0 

In the near future I plan to prepare a small HOWTO on how to reproduce these results. And I’ll probably write a big article after adding a module to MIPSfpga-plus for working with mmc / sdcard, finishing the bootloader and debugging everything that is needed for an autonomous launch. If someone needs "right now" - let me know.

MIPSfpga-plus and Altera MAX10 ADC

In June, I completed work on integrating the ADC, which is on board the Altera MAX10, into MIPSfpga-plus. The corresponding code is added to the main branch of the project [ L11 ], with documentation [ L12 ] and an example [ L13 ]. The module, in fact, is a converter between the AHB-Lite bus and Avalon-ST, made taking into account the specifics of a particular ADC. It is very simple in architecture - I tried to make its program interface as similar as possible to the Atmel ATmega88 microcontroller ADC.

Of course, there were no pitfalls, as there are 2 ADC channels available on the Terasic DE10-Lite FPGA (with independent sets of inputs on each), while wiring these inputs the second channel turned out to be entirely grounded, so parallel operation of channels on the DE10-Lite is impossible:

I would like to believe that MIPSfpga-plus will be used a little more often in academic projects where before it was necessary to use a microcontroller or a MAX10 + NIOS-II configuration for the sake of the integrated ADC.

Again, is a separate article needed, where work with ADCs is detailed? Or, in order to understand, is it enough for you to refer to the source code of the module, example, and documentation already given by me?

MIPSfpga-plus logo

Do you think the MIPSfpga-plus project is ripe enough for it to have its own recognizable logo? I probably spent more than a dozen hours on him, I already want him to be associated with some positive picture. For some reason, only Big Uh from the cartoon of the same name comes to mind (see KDPV), it is possible that because of his confederate, which is well associated with the originally educational orientation of the project. And in principle, this character is to me deeply likable.

What do you think about this topic? Maybe you can offer some alternative option or, suddenly, among the readers there is an artist who can portray a "cartoon character, remotely resembling the Big Ear, but not to the degree of confusion"?

Thanks

The author is grateful to the team of translators from David Harris and Sarah Harris “Digital Circuit Design and Computer Architecture” [ L2 ], from Imagination Technologies [ L1 ] for their academic license for modern processor core and educational materials, as well as personally to Yuri Panchul for YuriPanchul for his work on promoting MIPSfpga. Special thanks to Alexander Romanov (HSE, MIEM) [ L15 ] for a sensible and scrupulous approach to the schoolMIPS micro-architecture, as well as to all participants of the Young Russian Chip Architects mailing list who took part in the discussion.

Links

[L1] - Press release on the release of MIPSfpga 2.0 ;

[L2] - Digital circuit design and computer architecture ;

[L3] - Workshop on Computer Architecture Education (Toronto) ;

[L4] - Project MIPSfpga-plus on github ;

[L5] - Summer School for Programmers (Novosibirsk) ;

[L6] - Summer School for Programmers (Novosibirsk). Curriculum ;

[L7] - SchoolMIPS project on github ;

[L8] - Workshop on digital design and computer architecture (Tomsk) ;

[L9] - MIPSfpga support in the Linux kernel ;

[L10] - MIPSfpga and in-circuit debugging ;

[L11] - MIPSfpga-plus. Altera MAX10 ADC Support Module ;

[L12] - MIPSfpga-plus. Altera MAX10 ADC support module. Documentation ;

[L13] - MIPSfpga-plus. Altera MAX10 ADC support module. An example ;

[L14] - Practical experiences based on MIPSfpga ;

[L15] - Alexander Romanov's profile on the HSE website .