Chip for smart cameras ELISE - one of the most high-tech products in Russia in 2017. Developer fee and camera
Every Russian microelectronic company has a story why it is the best and most advanced. In English, this is called "claim to fame" - "application for fame." Some Russian companies are famous for the original architecture and / or CPU microarchitecture, others for the system-on-chip designed in Russia, and others for blocks designed in Russia that have been licensed to Western companies.
The Russian company ELVEES (ELVEES), which historically specialized in space electronics, DSP and hardware-supported pattern recognition, has a current “application for fame” in the joint Russian-British-US-Taiwan chip for “smart cameras” called ELISE. Engineers in Zelenograd near Moscow designed important video processing units and GNSS inside this chip , which were then cross-licensed by the British-American Imagination Technologies .
The Elvis units are integrated with three dissimilar processor cores: a 1.2 GHz dual-core cluster of superscalar MIPS P5607 cores (Apache) running Linux, a MIPS interAptiv (1 GHz) processor-supported processor and a small auxiliary processor with hardware-supported virtualization MIPS M5150 (Virtuoso).
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The other day, two products with an ELISE chip — a developer board and a three-dimensional binocular camera — fell into my hands. Elvisovtsy also gave me a list of 10 pages, what is on the board, what is inside the chip, and what software is supported for this. Unfortunately, they did not allow me to put these pages on the Internet, so I will retell something in my own words, as well as add info about the used kernels, after which you can ask the rest of Elvis yourself.
In the photos below are some of the engineers involved in the project. The girl on the left designed the part of the load-store unit in MIPS P5607, the young man in the green t-shirt wrote the interface models of the tires, and the comrade in the checkered shirt was the architect of the software ecosystem:
Fee large:
Camera:
ELVIS issued a press release on the ELISE chip a year ago, in May 2016 :
There are a lot of different blocks on the chip, including the PowerVR Clyde (GX6250) graphics processor and the heavy DSP — an 8-core VLIW SIMD ELVEES Velcore2, but I’ll only talk about the cores of conventional processors, which are three different classes on the chip. Why do we need different classes of processors, you can see in Charles slides, about which there is a post on Habré ( Development → You can download materials from Nanometer ASIC workshop (RUSNANO / MISiS / Imagination Technologies) - educational program on everything about chips ). I'll bring one slide from there:
The most efficient general-purpose processor (application processor) on an ELISE chip is the core of the MIPS P5607, codenamed “Apache”. It operates at a frequency of 1.2 GHz and has a high CoreMark. MIPS P5607 is a superscalar core with extraordinary execution of instructions and vector operations:
The two MIPS P5600 “Apache” cores are connected on the Elvis SoC to a dual-core cluster with a common second-level cache and a coherence manager that uses the MESI protocol to ensure consistency of the first-level cache states in the cores:
The next processor on the ELISE chip is the MIPS interAptiv core, which is synthesized at 1 GHz. This core is optimized for performance (performance / milliwatts). Elvis use this core for sound processing. In addition to Elvis, similar companies like MediaTek, which uses the previous version of the same micro-architecture in the MT7688 chip for the Internet of things, are in love.
MIPS interAptiv has an interesting feature - hardware support for multithreading, which originated in the predecessor of MIPS interAptiv - the core of MIPS 34K. I have a couple of slides about MIPS 34K and a clipping from The Microprocessor Report, which illustrate the idea:
The Elvis chip still has the MIPS M5150 core codenamed "Virtuoso". It is synthesized at a frequency of 600 MHz. This is a simple compact low-power core with a consistent five-stage pipeline. MIPS M5150 in this SoC is used as a controller for something undemanding (housekeeping, “maid” I mean):
In the MIPS M5150 core, there is an option for the DSP extension, although I don’t know for sure if Elvis members used this option. DSP extension allows limited vector instructions, integer fixed-point operations with saturation arithmetic, etc. This is certainly not a heavy DSP (which is already on an Elvis chip), but for some tasks it’s convenient:
The “claim to fame” of the MIPS M5150 core is the world's only small core of the microcontroller class that implements hardware support for virtualization. What for? As I already wrote , virtualization on such kernels is convenient for security. Even on a small chip for IoT, let's say the built-in Linux can work at the same time and say a very secure code for working with financial transactions. Now, if a user installs a hacked operating system, it will not be able to access another OS that performs critical operations, because there is a hypervisor between the two OSs. This becomes especially important in the case of the Internet of things, when an iron or a toaster thrown into the home network can theoretically exchange information with the host’s host computer.
For more information about virtualization, see the post Development → We invent a name for the new hypervisor for the MIPS architecture with hardware-supported virtualization ">
The ELVIS office is located in Zelenograd near Moscow, in the building in the center of the picture below, across the street from the MIET Institute, from which ELVIS draws personnel (as well as from MEPI, MIPT and other places). You can request information from Elvis employees, ever get a fee from them and do something on it (in order to photograph a fee with a girl, I had to temporarily take the fee from another colleague who is now porting to the Android board. You can also pay something to sport or program something built-in, graphical and recognition on it, although I don’t know when Elvis people will distribute these cards widely).
The Russian company ELVEES (ELVEES), which historically specialized in space electronics, DSP and hardware-supported pattern recognition, has a current “application for fame” in the joint Russian-British-US-Taiwan chip for “smart cameras” called ELISE. Engineers in Zelenograd near Moscow designed important video processing units and GNSS inside this chip , which were then cross-licensed by the British-American Imagination Technologies .
The Elvis units are integrated with three dissimilar processor cores: a 1.2 GHz dual-core cluster of superscalar MIPS P5607 cores (Apache) running Linux, a MIPS interAptiv (1 GHz) processor-supported processor and a small auxiliary processor with hardware-supported virtualization MIPS M5150 (Virtuoso).
')
The other day, two products with an ELISE chip — a developer board and a three-dimensional binocular camera — fell into my hands. Elvisovtsy also gave me a list of 10 pages, what is on the board, what is inside the chip, and what software is supported for this. Unfortunately, they did not allow me to put these pages on the Internet, so I will retell something in my own words, as well as add info about the used kernels, after which you can ask the rest of Elvis yourself.
In the photos below are some of the engineers involved in the project. The girl on the left designed the part of the load-store unit in MIPS P5607, the young man in the green t-shirt wrote the interface models of the tires, and the comrade in the checkered shirt was the architect of the software ecosystem:
Fee large:
Camera:
ELVIS issued a press release on the ELISE chip a year ago, in May 2016 :
There are a lot of different blocks on the chip, including the PowerVR Clyde (GX6250) graphics processor and the heavy DSP — an 8-core VLIW SIMD ELVEES Velcore2, but I’ll only talk about the cores of conventional processors, which are three different classes on the chip. Why do we need different classes of processors, you can see in Charles slides, about which there is a post on Habré ( Development → You can download materials from Nanometer ASIC workshop (RUSNANO / MISiS / Imagination Technologies) - educational program on everything about chips ). I'll bring one slide from there:
The most efficient general-purpose processor (application processor) on an ELISE chip is the core of the MIPS P5607, codenamed “Apache”. It operates at a frequency of 1.2 GHz and has a high CoreMark. MIPS P5607 is a superscalar core with extraordinary execution of instructions and vector operations:
The two MIPS P5600 “Apache” cores are connected on the Elvis SoC to a dual-core cluster with a common second-level cache and a coherence manager that uses the MESI protocol to ensure consistency of the first-level cache states in the cores:
The next processor on the ELISE chip is the MIPS interAptiv core, which is synthesized at 1 GHz. This core is optimized for performance (performance / milliwatts). Elvis use this core for sound processing. In addition to Elvis, similar companies like MediaTek, which uses the previous version of the same micro-architecture in the MT7688 chip for the Internet of things, are in love.
MIPS interAptiv has an interesting feature - hardware support for multithreading, which originated in the predecessor of MIPS interAptiv - the core of MIPS 34K. I have a couple of slides about MIPS 34K and a clipping from The Microprocessor Report, which illustrate the idea:
The Elvis chip still has the MIPS M5150 core codenamed "Virtuoso". It is synthesized at a frequency of 600 MHz. This is a simple compact low-power core with a consistent five-stage pipeline. MIPS M5150 in this SoC is used as a controller for something undemanding (housekeeping, “maid” I mean):
In the MIPS M5150 core, there is an option for the DSP extension, although I don’t know for sure if Elvis members used this option. DSP extension allows limited vector instructions, integer fixed-point operations with saturation arithmetic, etc. This is certainly not a heavy DSP (which is already on an Elvis chip), but for some tasks it’s convenient:
The “claim to fame” of the MIPS M5150 core is the world's only small core of the microcontroller class that implements hardware support for virtualization. What for? As I already wrote , virtualization on such kernels is convenient for security. Even on a small chip for IoT, let's say the built-in Linux can work at the same time and say a very secure code for working with financial transactions. Now, if a user installs a hacked operating system, it will not be able to access another OS that performs critical operations, because there is a hypervisor between the two OSs. This becomes especially important in the case of the Internet of things, when an iron or a toaster thrown into the home network can theoretically exchange information with the host’s host computer.
For more information about virtualization, see the post Development → We invent a name for the new hypervisor for the MIPS architecture with hardware-supported virtualization ">
The ELVIS office is located in Zelenograd near Moscow, in the building in the center of the picture below, across the street from the MIET Institute, from which ELVIS draws personnel (as well as from MEPI, MIPT and other places). You can request information from Elvis employees, ever get a fee from them and do something on it (in order to photograph a fee with a girl, I had to temporarily take the fee from another colleague who is now porting to the Android board. You can also pay something to sport or program something built-in, graphical and recognition on it, although I don’t know when Elvis people will distribute these cards widely).
Source: https://habr.com/ru/post/329864/
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