MIPSfpga and UART

It has been a little over a month since I ported the open source module UART16550 to the AHB-Lite bus. Writing about it at that time was somewhat not logical, since the article about the MIPSfpga interrupts has not yet been published.

If you are an experienced developer, then only one useful news for you: UART16550 added to the MIPSfpga-plus system, you can not read further. And those who are interested in the disassembled example of using this module are welcome under cat.

Introduction

It is assumed that the reader:

familiar with the subject area in the Harris-Harris volume [ L1 ];
has access to the source codes MIPSfpga [ L2 ] and mipsfpga-plus [ L3 ];
has some programming experience in microcontrollers (of any architecture), including the use of a UART. Refresh what the UART is like here [ L4 ];

What is UART16550

The history of the appearance of this chip is well described in [ L5 ], you can find documentation on it in google [ L6 ], something else is important for us:

it has become extremely widespread;
working with it is supported by the Linux kernel;
for it has long been an open source implementation on verilog [ L7 , L8 , L9 ], but for the Wishbone bus;
The price of porting this implementation to the AHB-Lite bus used in MIPSfpga is about 100 lines of code [ S1 ]:

mfp_ahb_lite_uart16550

module mfp_ahb_lite_uart16550( //ABB-Lite side input HCLK, input HRESETn, input [ 31 : 0 ] HADDR, input [ 2 : 0 ] HBURST, input HMASTLOCK, // ignored input [ 3 : 0 ] HPROT, // ignored input HSEL, input [ 2 : 0 ] HSIZE, input [ 1 : 0 ] HTRANS, input [ 31 : 0 ] HWDATA, input HWRITE, output reg [ 31 : 0 ] HRDATA, output HREADY, output HRESP, input SI_Endian, // ignored //UART side input UART_SRX, // UART serial input signal output UART_STX, // UART serial output signal output UART_RTS, // UART MODEM Request To Send input UART_CTS, // UART MODEM Clear To Send output UART_DTR, // UART MODEM Data Terminal Ready input UART_DSR, // UART MODEM Data Set Ready input UART_RI, // UART MODEM Ring Indicator input UART_DCD, // UART MODEM Data Carrier Detect //UART internal output UART_BAUD, // UART baudrate output output UART_INT // UART interrupt ); parameter S_INIT = 0, S_IDLE = 1, S_READ = 2, S_WRITE = 3; reg [ 1:0 ] State, Next; assign HRESP = 1'b0; assign HREADY = (State == S_IDLE); always @ (posedge HCLK) begin if (~HRESETn) State <= S_INIT; else State <= Next; end reg [ 2:0 ] ADDR_old; wire [ 2:0 ] ADDR = HADDR [ 4:2 ]; wire [ 7:0 ] ReadData; parameter HTRANS_IDLE = 2'b0; wire NeedAction = HTRANS != HTRANS_IDLE && HSEL; always @ (*) begin //State change decision case(State) default : Next = S_IDLE; S_IDLE : Next = ~NeedAction ? S_IDLE : ( HWRITE ? S_WRITE : S_READ ); endcase end always @ (posedge HCLK) begin case(State) S_INIT : ; S_IDLE : if(HSEL) ADDR_old <= ADDR; S_READ : HRDATA <= { 24'b0, ReadData}; S_WRITE : ; endcase end wire [ 7:0 ] WriteData = HWDATA [ 7:0 ]; wire [ 2:0 ] ActionAddr; wire WriteAction; wire ReadAction; reg [ 10:0 ] conf; assign { ReadAction, WriteAction, ActionAddr } = conf; always @ (*) begin //io case(State) default : conf = { 2'b00, 8'b0 }; S_READ : conf = { 2'b10, ADDR }; S_WRITE : conf = { 2'b01, ADDR_old }; endcase end // Registers uart_regs regs( .clk ( HCLK ), .wb_rst_i ( ~HRESETn ), .wb_addr_i ( ActionAddr ), .wb_dat_i ( WriteData ), .wb_dat_o ( ReadData ), .wb_we_i ( WriteAction ), .wb_re_i ( ReadAction ), .modem_inputs ( { UART_CTS, UART_DSR, UART_RI, UART_DCD } ), .stx_pad_o ( UART_STX ), .srx_pad_i ( UART_SRX ), .rts_pad_o ( UART_RTS ), .dtr_pad_o ( UART_DTR ), .int_o ( UART_INT ), .baud_o ( UART_BAUD ) ); endmodule

Main features of the implementation

The project [ L8 ], which, in turn, is based on [ L7 , L9 ], was taken as the base solution;
compared to the basic solution, the code associated with the Wishbone bus is excluded from the project. It is replaced by the corresponding interface module for AHB-Lite (mfp_ahb_lite_uart16550) [ S1 ];
All code borrowed from the base project is located in the uart16550 [ S2 ] directory;
The mfp_ahb_lite_uart16550 module is permanently included in the system; the MFP_USE_DUPLEX_UART [ S3 ] option in the mfp_ahb_lite_matrix_config.vh file determines the availability of the UART_SRX and UART_STX signals ;
For the already existing UART_RX and UART_TX signals , the following order of use is provided:
UART_RX - regardless of the mode, it is used only to load the firmware into the system memory, as it was before (the mfp_uart_receiver module, not applicable to the UART16550). If the MFP_USE_DUPLEX_UART option is not active, then the UART_TX is used to transfer data from the UART16550 to the outside; reception in this case is not available. If the option MFP_USE_DUPLEX_UART is active, then UART_TX is not used; UART_SRX and UART_STX [ S4 ] are used to transfer data from / to mfp_ahb_lite_uart16550;
output of the modem control interface to the top level of the module was not made. Corresponding lines are available in the interface ahb_lite_uart16550 and can be used if necessary ( UART_RTS, UART_CTS, UART_DTR, UART_DSR, UART_RI, UART_DCD ) [ S5 ];
the interrupt signal ( UART_INT ) is connected to the hw3 input (SI_Int signal [3] ) for backward and vector compatibility modes. And to eic5 (signal EIC_input [5] ) for an external interrupt controller [ S6 ];
when started in simulation mode, the UART_STX line is closed to UART_SRX [ S7 ];
The performance of the solution obtained in the simulation mode was tested using Modelsim;
performance on the hardware tested on the board Terasic DE10-Lite [ L10 ];
As an example of working with the UART16550, two programs were written: 05_uart [ S8 ] and 08_uart_irq [ S9 ]: after resetting, the uart (8n1, 115200) setting is performed, the greeting is sent, and the code of each received symbol is displayed on the LED and 7-segment indicators. When launched on the board, each character received by uart is sent back;
debugging of the developed module is available "in isolation" from the mipsfpga + code within the project [ L11 ];
For software configuration of the module, use the base project documentation, [ D1 ]. I recommend to familiarize with it fluently to better understand the example given below;
AHB-Lite bus operation is described in detail in [ D2 ];

Example

Start order

check that the following setting [ S3 ] is set in the file mfp_ahb_lite_matrix_config.vh:
```
 `define MFP_USE_DUPLEX_UART 
```
go to the directory with the program: mipsfpga-plus / programs / 05_uart [ S8 ], or 08_uart_irq [ S9 ];
in the main.c file install [ S10 ]:
```
 #define RUNTYPE SIMULATION 
```

build the program and run it in the simulator:

 02_compile_and_link.bat 05_generate_verilog_readmemh_file.bat 06_simulate_with_modelsim.bat

after the completion of the simulation script, press "no" to prevent the simulator from closing;
how this code works "on hardware" can be seen on the capital gif-ke.

Program Description and System Configuration

Since the example 08_uart_irq provides, in addition to setting up the UART16550 itself, the use of the interrupts generated by it, this configuration is discussed below;
The directives for working with the registers of the controller are in the header file uart16550.h [ S11 ];

At startup, the UART16550 setup [ S12 ]:

 void uartInit(uint16_t divisor) { // 8n1 uart mode MFP_UART_LCR = MFP_UART_LCR_8N1; // Divisor Latches access enable MFP_UART_LCR |= MFP_UART_LCR_LATCH; // Divisor LSB MFP_UART_DLL = divisor & 0xFF; // Divisor MSB MFP_UART_DLH = (divisor >> 8) & 0xff; // Divisor Latches access disable MFP_UART_LCR &= ~MFP_UART_LCR_LATCH; //enable Received Data available interrupt MFP_UART_IER = MFP_UART_IER_RDA; //set 4 byte Receiver FIFO Interrupt trigger level MFP_UART_FCR = MFP_UART_FCR_ITL4; }

setting interrupts [ S13 ] (detailed in [ L12 ]):

 void mipsInterruptInit(void) { // Status.BEV 0 - vector interrupt mode mips32_bicsr (SR_BEV); // Cause.IV, 1 - special int vector (0x200) // where 0x200 - base for others interrupts; mips32_biscr (CR_IV); // get IntCtl reg value uint32_t intCtl = mips32_getintctl(); // set interrupt table vector spacing (0x20 in our case) // see exceptions.S for details mips32_setintctl(intCtl | INTCTL_VS_32); // interrupt enable, HW3 unmasked mips32_bissr (SR_IE | SR_HINT3); }

Interrupt processing involves checking that it is caused precisely by the presence of data in the incoming FIFO [ S14 ]:

 // uart interrupt handler void __attribute__ ((interrupt, keep_interrupts_masked)) __mips_isr_hw3 () { // Receiver Data available interrupt handler if(MFP_UART_IIR & MFP_UART_IIR_RDA) uartReceive(); }

followed by their reading (until the FIFO is empty) and the output [ S15 ]:

 void uartReceive(void) { // is there something in receiver fifo? while (MFP_UART_LSR & MFP_UART_LSR_DR) { // data receive uint8_t data = MFP_UART_RXR; receivedDataOutput(data); #if RUNTYPE == HARDWARE uartTransmit(data); #endif } }

if the work goes on "hardware", then all the data is sent back [ S16 ]:

 void uartTransmit(uint8_t data) { // waiting for transmitter fifo empty while (!(MFP_UART_LSR & MFP_UART_LSR_TFE)); // data transmit MFP_UART_TXR = data; }

Below is the result of the program. Since when setting up the module we set the interrupt triggering mode after receiving 4 characters, the transmission is temporarily interrupted for reception. The remaining characters were received by us after another similar interruption, but which was already caused not by the presence of 4 characters in the queue, and not by an empty queue and timeout (the controller realized that there would be no more characters and informed that the queue was not empty);
for program 05_uart, reception is performed after the transfer is completed, all this time the received data is waiting in the receiver's FIFO:

Thanks

The author is grateful to the team of translators of the textbook by David Harris and Sarah Harris “Digital Circuit Design and Computer Architecture”, by Imagination Technologies for the academic license for a modern processor core and personally for Yuri Panchul YuriPanchul for his work on promoting MIPSfpga.