How does the FIFO work
FIFO is one of the key elements of digital technology. This is the first-in-first-out memory. As a developer of FPGAs, I am surrounded everywhere. Actually, I only do that I take data from one FIFO and transfer it to another. But how does it work? In modern CADs, of course, there are already ready-made elements, Altera has wonderful megafunctions. Xilinx has a Core Generator. But what if something does not suit the standard solutions? The answer is one - to figure it out and write it yourself.
On the Internet there are a large number of articles about FIFO, and when I came across a very good and sensible article. Unfortunately, I did not find it now. Next is my personal experience in creating and using the FIFO component. The finished item is on Github in the fpga_components project. Its component was required for several reasons:
So what is FIFO. In general, this is a two-port memory, two address counters and two machines for reading and writing data.
')
One of the main uses of FIFO is to transfer data from one clock frequency to another. This determines such a scheme. With one clock frequency for recording and reading, automata can be simplified.
Let's look at the external ports of the FIFO component:
Component setting:
The names of the ports are quite obvious, a few comments on the flags:
FIFO flags are passed as bl_fifo_flag; Type Definition:
Note that negative logic is used. Learned? Yes, I am one of those dinosaurs who worked with TTL on the series 155, 533, 1533 and individual FIFO microcircuits. So these flags are familiar to me, they were made many years ago and are still used.
The ef flag indicates that the FIFO is empty. If ef = 1, then one word can be read from the FIFO.
The pae flag indicates that the FIFO is almost empty. How almost determines the parameter FIFO_PAE. If pae = 1, then no more than FIFO_PAE can be read from a FIFO.
The hf flag indicates that the FIFO is half full.
The paf flag indicates that the FIFO is almost complete. How almost determines the parameter FIFO_PAF. If paf = 1, then no more than FIFO_PAF words can be written to the FIFO.
The ff flag is full FIFO. If ff = 0, then it cannot be written to the FIFO.
Ovr flag - overflow. If ovr = 1, then this means that an entry was made in the full FIFO
Flag und - underflow. If und = 1, then this means that a read from an empty FIFO has occurred.
It is quite obvious that when writing to the FIFO, we need to write the word into two-port memory and increase the record count. Or, first increase and then write. And during a read operation, you need to fix the data at the output and increase the reading counter. But then you need to solve the following questions:
It is quite obvious that the answers to all these questions in the analysis of counters are addresses for writing and reading. But these counters operate at different frequencies. This is where the differences in implementations begin. I applied a symmetric scheme of transferring the values of counters to another clock domain. As a result, it turned out that each of the automata of reading and writing has the value of its counter and the delayed value of the other counter. From these values, automata form their flags and the value of the number of words in the FIFO. This can be represented on the structural diagram:
It should be clearly understood that the revision node (in the project, this is the ctrl_retack_counter_m12 component) transfers data with a delay of several cycles. Therefore, FIFO states also change with a delay. For example, if the FIFO is empty and one word is written to it, then the ef = 1 flag will appear with some delay. The same applies to word number outputs in the FIFO. For example, if 16 words are written into an empty FIFO, then in the process of recording, the output cnt_wr will take values 0,1,2,3, ... 16 (this is if no reading is made from the FIFO), but the output cnt_rd will take values for example: 0, 5, 8, 12, 16. The exact order will depend on the frequency ratio and cannot be predicted. This is a fundamental property of the FIFO that works at different frequencies. Although depending on the synchronization scheme may be different nuances.
The definition of an empty and full FIFO is made on the analysis of address counters. And I have two addresses for writing (current and next) and two addresses for reading, also current and next. In the cl_fifo_control_m12 component, these are the w_adr, w_next_adr and r_adr, r_next_adr signals; The ratio of addresses in different states is shown in the figures below.
In the initial state, w_adr = 0, r_adr = 0, w_next_adr = 1, r_next_adr = 1. If w_adr = r_adr, then the FIFO is empty.
When writing, the data word is recorded at w_adr and the address of the record is incremented.
After several such, the value of w_adr will be transferred to w_adr_to_rd (will go to the clock domain clk_rd) and the fact that r_adr and w_adr_to_rd will not match will be set to ef = 1, i.e. From the FIFO, you can read the data word. However, one word is not enough; in order to obtain a high transfer rate, it is necessary to work with a data block. And here it is required to use the PAE flag. When the FIFO_PAE of words is written to the FIFO, the pae = 1 flag will be set and the data block can be read immediately. This is the main mode of operation with a DMA channel.
If the write speed is greater than the read speed, then the write address will catch up with the read address:
In this case, w_next_adr will be equal to r_adr, or rather, r_adr_to_wr (we can only compare values on our own clock domain). This means that the FIFO is complete and cannot be recorded further, so as not to spoil the already recorded data. It should be noted that to connect the ADC is a common situation. We have this mode is called a one-time collection through the FIFO. In this mode, the ADC writes data at high speed to the FIFO, and the slow processor reads this data. At the same time, we know that only the data block that corresponds to the size of the FIFO will be valid. Usually, DMA channel is programmed to this size. After reading the data, the FIFO is reset and everything is repeated again. Here in this mode it is crucial that the record in the full FIFO does not spoil the previous data.
If you want to write data in blocks, you need to use the PAF flag. If paf = 1, then FIFO_PAF words can be written to the FIFO.
The values of the PAE and PAF flags must be chosen from the requirements of the DMA controller to which the FIFO is connected. For example, for PCI Express, we use a data block of 4 KB in size. This is 256 words for 128 digits. I set the size of the PAE flag to 272. Ie slightly more than 256. This is what I do intentionally to prevent the FIFO from being devastated. Well, I do not trust the formation of flags.
And how is the determination of the number of words in the FIFO? Everything is quite simple - you should subtract the address of reading from the address of the record. The address is a multiple of degree 2, so the subtraction will go modulo 2 ^ N; Since we have two pairs of addresses, then we will have two meanings of the number of words in one FIFO (maybe this is somehow connected with quantum mechanics?).
The values of the PAE and HF flags (by reading) are formed from r_cnt. The values of PAF and HF (by record) are formed from w_cnt.
The main reason for which it was necessary to develop its FIFO component is the need to implement a cyclic mode for working on a DAC. In this mode, a data block is recorded, it can be of any size, of course, not exceeding the size of the FIFO. And then reading begins, and after the last written word is issued, the transition to the first word occurs immediately. This allows you to connect a slow processor to a fast DAC. The FIFO component has two inputs for cyclic mode. rt_mode = 1 means that after issuing the last recorded word, go to the zero address.
But the rt input is needed a little for another. The presence of rt = 1 allows you to transfer the FIFO to a zero address at an arbitrary point in time. Sometimes it is also used here.
In the fpga_components project, two FIFOs are presented:
cl_fifo_x64_v7 was developed and published for a long time. It has also been used for a long time and proved its efficiency. It uses the component Generated Core Generator as dual-port memory. Different sizes of FIFO require their own components, for example in the fpga_components \ src \ fifo \ fifo_v7 \ coregen directory there are four components
And this is all only for tires with a width of 64 bits. Other tires and other sizes require their own components. We did them on the sly and by now we have a big pile, with which it’s already inconvenient to work. Alexander Kapitanov ( capitanov ) drew attention to this and proposed an elegant solution - to make a fully synthesized FIFO. He implemented it in his project: github.com/capitanov/adc_configurator Component: ctrl_fifo_config . The basic idea is to use the following VHDL construction:
This design will be synthesized into dual-port memory. The idea is beautiful and as a result of the cl_fifo_x64_v7 refinement, it turned out FIFO cl_fifo_m12 .
It is not enough to write a FIFO, you need to check its operation. For verification, the approach taken in developing PROTEQ is used, which can be found in my previous article .
There is a tb_00 component that has customizable parameters.
It allows you to check the flow of data through the FIFO at various ratios of clock frequencies and the trigger levels of the PAE and PAF flags. There are also test case components:
As a result, the following test report is generated:
Of course, for each test saved and its report.
For example:
If necessary, tests will be supplemented. I want to note that I use the PCK_FIO package to display text in the console. It dramatically simplifies text output.
For example, the output of the results looks like this:
It looks like C.
In the end, I believe that we have an elegant component, convenient enough for practical work.
On the Internet there are a large number of articles about FIFO, and when I came across a very good and sensible article. Unfortunately, I did not find it now. Next is my personal experience in creating and using the FIFO component. The finished item is on Github in the fpga_components project. Its component was required for several reasons:
- FIFO XIlinx does not know how to work in retransmit mode - this is the main reason
- FIFO Xilinx requires the creation of a component with the specified parameters - we have divorced too many different components.
- Xilinx FIFO has an error — if a reset signal arrives at the same time as the data recording signal, then one word stuck in the FIFO. This we certainly went around, but still unpleasant.
So what is FIFO. In general, this is a two-port memory, two address counters and two machines for reading and writing data.
')
One of the main uses of FIFO is to transfer data from one clock frequency to another. This determines such a scheme. With one clock frequency for recording and reading, automata can be simplified.
Let's look at the external ports of the FIFO component:
cl_fifo_m12
component cl_fifo_m12 is generic( FIFO_WIDTH : in integer:=64; -- FIFO FIFO_SIZE : in integer:=4096; -- FIFO FIFO_PAF : in integer:=16; -- PAF FIFO_PAE : in integer:=544 -- PAE ); port( -- reset_p : in std_logic; -- 1 - -- clk_wr : in std_logic; -- data_in : in std_logic_vector( FIFO_WIDTH-1 downto 0 ); -- data_en : in std_logic; -- 1 - fifo flag_wr : out bl_fifo_flag; -- fifo, clk_wr cnt_wr : out std_logic_vector( 15 downto 0 ); -- -- clk_rd : in std_logic; -- data_out : out std_logic_vector( FIFO_WIDTH-1 downto 0 ); -- data_rd : in std_logic:='0'; -- 1 - fifo, flag_rd : out bl_fifo_flag; -- fifo, clk_rd cnt_rd : out std_logic_vector( 15 downto 0 ); -- rt : in std_logic:='0'; -- 1 - rt_mode : in std_logic:='0' -- 1 - FIFO ); end component; Component setting:
- FIFO_WIDTH - FIFO width, can be any.
- FIFO_SIZE - the number of words in the FIFO, is a power of two, from 64 to 65536. If you need a larger size, then you need to make a composite FIFO.
- FIFO_PAF - the level of operation of the almost full FIFO flag.
- FIFO_PAE - the trigger level of the almost empty FIFO flag, the flags will be next.
The names of the ports are quite obvious, a few comments on the flags:
FIFO flags are passed as bl_fifo_flag; Type Definition:
type bl_fifo_flag is record ef : std_logic; -- 0 - FIFO pae : std_logic; -- 0 - FIFO hf : std_logic; -- 0 - FIFO paf : std_logic; -- 0 - FIFO ff : std_logic; -- 0 - FIFO ovr : std_logic; -- 1 - FIFO und : std_logic; -- 1 - FIFO end record; Note that negative logic is used. Learned? Yes, I am one of those dinosaurs who worked with TTL on the series 155, 533, 1533 and individual FIFO microcircuits. So these flags are familiar to me, they were made many years ago and are still used.
The ef flag indicates that the FIFO is empty. If ef = 1, then one word can be read from the FIFO.
The pae flag indicates that the FIFO is almost empty. How almost determines the parameter FIFO_PAE. If pae = 1, then no more than FIFO_PAE can be read from a FIFO.
The hf flag indicates that the FIFO is half full.
The paf flag indicates that the FIFO is almost complete. How almost determines the parameter FIFO_PAF. If paf = 1, then no more than FIFO_PAF words can be written to the FIFO.
The ff flag is full FIFO. If ff = 0, then it cannot be written to the FIFO.
Ovr flag - overflow. If ovr = 1, then this means that an entry was made in the full FIFO
Flag und - underflow. If und = 1, then this means that a read from an empty FIFO has occurred.
It is quite obvious that when writing to the FIFO, we need to write the word into two-port memory and increase the record count. Or, first increase and then write. And during a read operation, you need to fix the data at the output and increase the reading counter. But then you need to solve the following questions:
- How to determine that the FIFO is full or not complete, i.e. Can I write to it?
- How to determine if the FIFO is empty or not empty? Those. Can I read from it?
- How to form the flags PAE, PAF, HF?
- What is the number of words in the FIFO?
It is quite obvious that the answers to all these questions in the analysis of counters are addresses for writing and reading. But these counters operate at different frequencies. This is where the differences in implementations begin. I applied a symmetric scheme of transferring the values of counters to another clock domain. As a result, it turned out that each of the automata of reading and writing has the value of its counter and the delayed value of the other counter. From these values, automata form their flags and the value of the number of words in the FIFO. This can be represented on the structural diagram:
It should be clearly understood that the revision node (in the project, this is the ctrl_retack_counter_m12 component) transfers data with a delay of several cycles. Therefore, FIFO states also change with a delay. For example, if the FIFO is empty and one word is written to it, then the ef = 1 flag will appear with some delay. The same applies to word number outputs in the FIFO. For example, if 16 words are written into an empty FIFO, then in the process of recording, the output cnt_wr will take values 0,1,2,3, ... 16 (this is if no reading is made from the FIFO), but the output cnt_rd will take values for example: 0, 5, 8, 12, 16. The exact order will depend on the frequency ratio and cannot be predicted. This is a fundamental property of the FIFO that works at different frequencies. Although depending on the synchronization scheme may be different nuances.
The definition of an empty and full FIFO is made on the analysis of address counters. And I have two addresses for writing (current and next) and two addresses for reading, also current and next. In the cl_fifo_control_m12 component, these are the w_adr, w_next_adr and r_adr, r_next_adr signals; The ratio of addresses in different states is shown in the figures below.
In the initial state, w_adr = 0, r_adr = 0, w_next_adr = 1, r_next_adr = 1. If w_adr = r_adr, then the FIFO is empty.
When writing, the data word is recorded at w_adr and the address of the record is incremented.
After several such, the value of w_adr will be transferred to w_adr_to_rd (will go to the clock domain clk_rd) and the fact that r_adr and w_adr_to_rd will not match will be set to ef = 1, i.e. From the FIFO, you can read the data word. However, one word is not enough; in order to obtain a high transfer rate, it is necessary to work with a data block. And here it is required to use the PAE flag. When the FIFO_PAE of words is written to the FIFO, the pae = 1 flag will be set and the data block can be read immediately. This is the main mode of operation with a DMA channel.
If the write speed is greater than the read speed, then the write address will catch up with the read address:
In this case, w_next_adr will be equal to r_adr, or rather, r_adr_to_wr (we can only compare values on our own clock domain). This means that the FIFO is complete and cannot be recorded further, so as not to spoil the already recorded data. It should be noted that to connect the ADC is a common situation. We have this mode is called a one-time collection through the FIFO. In this mode, the ADC writes data at high speed to the FIFO, and the slow processor reads this data. At the same time, we know that only the data block that corresponds to the size of the FIFO will be valid. Usually, DMA channel is programmed to this size. After reading the data, the FIFO is reset and everything is repeated again. Here in this mode it is crucial that the record in the full FIFO does not spoil the previous data.
If you want to write data in blocks, you need to use the PAF flag. If paf = 1, then FIFO_PAF words can be written to the FIFO.
The values of the PAE and PAF flags must be chosen from the requirements of the DMA controller to which the FIFO is connected. For example, for PCI Express, we use a data block of 4 KB in size. This is 256 words for 128 digits. I set the size of the PAE flag to 272. Ie slightly more than 256. This is what I do intentionally to prevent the FIFO from being devastated. Well, I do not trust the formation of flags.
And how is the determination of the number of words in the FIFO? Everything is quite simple - you should subtract the address of reading from the address of the record. The address is a multiple of degree 2, so the subtraction will go modulo 2 ^ N; Since we have two pairs of addresses, then we will have two meanings of the number of words in one FIFO (maybe this is somehow connected with quantum mechanics?).
The values of the PAE and HF flags (by reading) are formed from r_cnt. The values of PAF and HF (by record) are formed from w_cnt.
The main reason for which it was necessary to develop its FIFO component is the need to implement a cyclic mode for working on a DAC. In this mode, a data block is recorded, it can be of any size, of course, not exceeding the size of the FIFO. And then reading begins, and after the last written word is issued, the transition to the first word occurs immediately. This allows you to connect a slow processor to a fast DAC. The FIFO component has two inputs for cyclic mode. rt_mode = 1 means that after issuing the last recorded word, go to the zero address.
But the rt input is needed a little for another. The presence of rt = 1 allows you to transfer the FIFO to a zero address at an arbitrary point in time. Sometimes it is also used here.
In the fpga_components project, two FIFOs are presented:
- cl_fifo_x64_v7
- cl_fifo_m12
cl_fifo_x64_v7 was developed and published for a long time. It has also been used for a long time and proved its efficiency. It uses the component Generated Core Generator as dual-port memory. Different sizes of FIFO require their own components, for example in the fpga_components \ src \ fifo \ fifo_v7 \ coregen directory there are four components
- ctrl_dpram512x64_v7
- ctrl_dpram1024x64_v7
- ctrl_dpram8192x64_v7
- ctrl_dpram32768x64_v7
And this is all only for tires with a width of 64 bits. Other tires and other sizes require their own components. We did them on the sly and by now we have a big pile, with which it’s already inconvenient to work. Alexander Kapitanov ( capitanov ) drew attention to this and proposed an elegant solution - to make a fully synthesized FIFO. He implemented it in his project: github.com/capitanov/adc_configurator Component: ctrl_fifo_config . The basic idea is to use the following VHDL construction:
type RAM is array (integer range <>) of std_logic_vector(DATA_WIDTH-1 downto 0); signal Mem : RAM (0 to DATA_DEPTH-1); This design will be synthesized into dual-port memory. The idea is beautiful and as a result of the cl_fifo_x64_v7 refinement, it turned out FIFO cl_fifo_m12 .
It is not enough to write a FIFO, you need to check its operation. For verification, the approach taken in developing PROTEQ is used, which can be found in my previous article .
There is a tb_00 component that has customizable parameters.
tb_00
component tb_00 is generic( max_time : in time:=100 us; -- period_wr : in time; -- period_rd : in time; -- fifo_size : in integer; -- FIFO FIFO_PAF : in integer; -- PAF FIFO_PAE : in integer; -- PAE max_fifo0_pkg : in integer -- ); end component; It allows you to check the flow of data through the FIFO at various ratios of clock frequencies and the trigger levels of the PAE and PAF flags. There are also test case components:
- tc_00_01 - check the case when the write speed is greater than the read speed.
- tc_00_02 - and this is when the read speed is greater than the write speed.
As a result, the following test report is generated:
Global fifo_12 TC log: tc_00_01 PASSED tc_00_02 PASSED Of course, for each test saved and its report.
For example:
tc_00_01.log
# KERNEL: FIFO 0 - PKG= 1 6310 ns 0 ns ERROR: 0 SPEED: 0 # KERNEL: FIFO 0 - PKG= 2 12022 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 3 17734 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 4 23446 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 5 29158 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 6 34870 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 7 40582 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 8 46294 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 9 52006 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 10 57718 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 11 63430 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 12 69142 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 13 74854 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 14 80566 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 15 86278 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 16 91990 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 17 97702 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 18 103414 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 19 109126 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 20 114838 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 21 120550 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 22 126262 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 23 131974 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 24 137686 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 25 143398 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 26 149110 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 27 154822 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 28 160534 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 29 166246 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 30 171958 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 31 177670 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 32 183382 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 33 189094 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 34 194806 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 35 200518 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 36 206230 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 37 211942 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 38 217654 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 39 223366 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 40 229078 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 41 234790 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 42 240502 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 43 246214 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 44 251926 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 45 257638 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 46 263350 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 47 269062 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 48 274774 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 49 280486 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 50 286198 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 51 291910 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 52 297622 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 53 303334 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 54 309046 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 55 314758 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 56 320470 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 57 326182 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 58 331894 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 59 337606 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 60 343318 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 61 349030 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 62 354742 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 63 360454 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 64 366166 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 65 371878 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 66 377590 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 67 383302 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 68 389014 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 69 394726 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 70 400438 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 71 406150 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 72 411862 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 73 417574 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 74 423286 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 75 428998 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 76 434710 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 77 440422 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 78 446134 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 79 451846 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 80 457558 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 81 463270 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 82 468982 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 83 474694 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 84 480406 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 85 486118 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 86 491830 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 87 497542 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 88 503254 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 89 508966 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 90 514678 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 91 520390 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 92 526102 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 93 531814 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 94 537526 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 95 543238 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 96 548950 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 97 554662 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 98 560374 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG= 99 566086 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=100 571798 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=101 577510 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=102 583222 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=103 588934 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=104 594646 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=105 600358 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=106 606070 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=107 611782 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=108 617494 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=109 623206 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=110 628918 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=111 634630 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=112 640342 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=113 646054 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=114 651766 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=115 657478 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=116 663190 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=117 668902 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=118 674614 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=119 680326 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=120 686038 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=121 691750 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=122 697462 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=123 703174 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=124 708886 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=125 714598 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=126 720310 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=127 726022 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=128 731734 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=129 737446 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=130 743158 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=131 748870 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=132 754582 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=133 760294 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=134 766006 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=135 771718 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=136 777430 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=137 783142 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=138 788854 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=139 794566 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=140 800278 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=141 805990 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=142 811702 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=143 817414 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=144 823126 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=145 828838 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=146 834550 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=147 840262 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=148 845974 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=149 851686 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=150 857398 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=151 863110 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=152 868822 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=153 874534 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=154 880246 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=155 885958 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=156 891670 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=157 897382 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=158 903094 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=159 908806 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=160 914518 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=161 920230 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=162 925942 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=163 931654 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=164 937366 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=165 943078 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=166 948790 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=167 954502 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=168 960214 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=169 965926 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=170 971638 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=171 977350 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=172 983062 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=173 988774 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=174 994486 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=175 1000198 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=176 1005910 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=177 1011622 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=178 1017334 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=179 1023046 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=180 1028758 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=181 1034470 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=182 1040182 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=183 1045894 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=184 1051606 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=185 1057318 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=186 1063030 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=187 1068742 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=188 1074454 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=189 1080166 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=190 1085878 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=191 1091590 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=192 1097302 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=193 1103014 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=194 1108726 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=195 1114438 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=196 1120150 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=197 1125862 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=198 1131574 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=199 1137286 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=200 1142998 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=201 1148710 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=202 1154422 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=203 1160134 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=204 1165846 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=205 1171558 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=206 1177270 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=207 1182982 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=208 1188694 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=209 1194406 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=210 1200118 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=211 1205830 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=212 1211542 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=213 1217254 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=214 1222966 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=215 1228678 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=216 1234390 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=217 1240102 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=218 1245814 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=219 1251526 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=220 1257238 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=221 1262950 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=222 1268662 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=223 1274374 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=224 1280086 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=225 1285798 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=226 1291510 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=227 1297222 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=228 1302934 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=229 1308646 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=230 1314358 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=231 1320070 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=232 1325782 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=233 1331494 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=234 1337206 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=235 1342918 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=236 1348630 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=237 1354342 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=238 1360054 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=239 1365766 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=240 1371478 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=241 1377190 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=242 1382902 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=243 1388614 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=244 1394326 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=245 1400038 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=246 1405750 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=247 1411462 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=248 1417174 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=249 1422886 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=250 1428598 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=251 1434310 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=252 1440022 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=253 1445734 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=254 1451446 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=255 1457158 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: FIFO 0 - PKG=256 1462870 ns 5712 ns ERROR: 0 SPEED: 1368 # KERNEL: : 1463200 ns # KERNEL: FIFO 0 # KERNEL: : 256 # KERNEL: : 256 # KERNEL: : 0 # KERNEL: : 0 # KERNEL: : 1368 / # KERNEL: # KERNEL: # KERNEL: # KERNEL: TEST finished successfully # KERNEL: If necessary, tests will be supplemented. I want to note that I use the PCK_FIO package to display text in the console. It dramatically simplifies text output.
For example, the output of the results looks like this:
fprint( output, L, " : %r ns\n", fo(now) ); fprint( output, L, "FIFO 0 \n" ); fprint( output, L, " : %d\n", fo( rx0_result.pkg_rd ) ); fprint( output, L, " : %d\n", fo( rx0_result.pkg_ok ) ); fprint( output, L, " : %d\n", fo( rx0_result.pkg_error ) ); fprint( output, L, " : %d\n", fo( rx0_result.total_error ) ); fprint( output, L, " : %r /\n\n", fo( integer(rx0_result.velocity) ) ); It looks like C.
In the end, I believe that we have an elegant component, convenient enough for practical work.
Source: https://habr.com/ru/post/321674/
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