Ukrainian prompted the British to do a webinar for IoT developers for agriculture. And we will talk about the CPU inside
The ways of technology are inscrutable. Three months ago, a businessman from Ukraine Alexander Romanishin came to us in Silicon Valley. I went with Alexander to an exhibition for IoT developers, where we met David Harold from the British part of Imagination Technologies (the company that designed the PowerVR GPU inside the Apple iPhone).
Oleksandr saw David's MIPS Creator ci40 demo boards for smart farms, and he spent twenty minutes telling David that, starting with Poroshenko, the entire government of Ukraine personally wanted to cross over electronic technologies and agriculture in order to find the country's economic future. (Alexander is a senior audit company manager who analyzes and supports M & A transactions)
David took it all as literally as possible and this morning I received a letter from Chief David, from where I learned that they had done an online webinar in the UK on using the MIPS Creator ci40 to build a smart irrigation system , and Alexander’s colleagues can register for this seminar on Wednesday September 28 at 11 am, Silicon Valley at 9 pm, Kyiv time:
')
On this occasion, I want to dig deeper into the chip and tell about the history and features of the processor core in the device shown in the webinar. Inside MIPS Creator ci40 is a chip based on a multithreaded dual-core cluster MIPS interAptiv, advanced scion kernel MIPS 24KEc. The latter is now experiencing a second youth inside the Omega2, a Linux computer that has just entered the market , priced at $ 5 the size of a postage stamp . How does the MIPS interAptiv inside the MIPS Creator ci40 differ from the MIPS 24KEc inside the Omega2 in terms of the micro-architecture and how does it hurt the programmer?
First, a few words about MIPS 24KEc. In MIPS Technologies there are three lines of cores, like three bears in the tale of Leo Tolstoy :
In short, MIPS 24K is the basis of the 32-bit section of the middle line of MIPS Technologies cores. They have 8 pipeline stages (which is more than 5 and less than 15), there is a transition predictor (unlike MIPS M51xx, M62xx), but there is no superscalarity (unlike MIPS I6400, P5600, P6600).
After MIPS 24K, MIPS 34K was added to which hardware supported multithreading was added. This is a rather elegant solution for the following problem.
The fact is that in recent decades, the speed of arithmetic calculations in the processor has grown faster than the speed of memory access:
In our era, when a cache misses data, the processor could execute dozens of arithmetic instructions. How to make the processor not idle (idle time of this type can take up to 50% of the typical program execution time)? That's how:
A couple of pictures from an article in The Microprocessor Report magazine:
Hardware support for multithreading on a single core should not be confused with multi-core. However, they may be present both individually and in combination. MIPS interAptiv (like its predecessor MIPS 1004K) is a multi-core system with a coherence manager for first-level caches (so that different modified data does not lie in L1 caches of different cores):
MIPS interAptiv is a modern optimized version of the line that started with MIPS 24K. That it is in the built-in computer MIPS Creator ci40. Although there are two processor cores in it, multi-core Linux treats them as four, since each of the two cores internally processes two streams of commands - hardware-supported multithreading. While one tread waits during cache miss, the other can work - this achieves greater CPU usage. Ultimately, this structure leads to energy savings compared to systems with a large number of single-threaded cores:
UPD: In the comments to the post an interesting question arose about registers with multithreading. I had to mention this on the slides.
Yes, in MIPS interAptiv there are several sets of registers visible to the programmer, which are switched for each thread. This causes the size of the processor to increase by about 20%. But the registers for the tail of the conveyor do not need to be switched, since by this moment the values of the operands have already been read.
Here is a document that describes everything that happens in each part of the MIPS 34K pipeline (in MIPS interAptiv, it is very similar):
https://imagination-technologies-cloudfront-assets.s3.amazonaws.com/documentation/MD00534-2B-34K-SUM-01.13.pdf
More documents from there:
https://imgtec.com/mips/classic
Oh, and do not forget to register for the webinar:
Oleksandr saw David's MIPS Creator ci40 demo boards for smart farms, and he spent twenty minutes telling David that, starting with Poroshenko, the entire government of Ukraine personally wanted to cross over electronic technologies and agriculture in order to find the country's economic future. (Alexander is a senior audit company manager who analyzes and supports M & A transactions)
David took it all as literally as possible and this morning I received a letter from Chief David, from where I learned that they had done an online webinar in the UK on using the MIPS Creator ci40 to build a smart irrigation system , and Alexander’s colleagues can register for this seminar on Wednesday September 28 at 11 am, Silicon Valley at 9 pm, Kyiv time:
')
On this occasion, I want to dig deeper into the chip and tell about the history and features of the processor core in the device shown in the webinar. Inside MIPS Creator ci40 is a chip based on a multithreaded dual-core cluster MIPS interAptiv, advanced scion kernel MIPS 24KEc. The latter is now experiencing a second youth inside the Omega2, a Linux computer that has just entered the market , priced at $ 5 the size of a postage stamp . How does the MIPS interAptiv inside the MIPS Creator ci40 differ from the MIPS 24KEc inside the Omega2 in terms of the micro-architecture and how does it hurt the programmer?
First, a few words about MIPS 24KEc. In MIPS Technologies there are three lines of cores, like three bears in the tale of Leo Tolstoy :
In this house lived three bears. One bear was the father, his name was Mikhail Ivanovich. He was big, shaggy and superscalar (MIPS P5600, P6600). The other was the bear. It was smaller, but more power-efficient, and her name was Nastasya Petrovna (MIPS 24K, interAptiv, I6400). The third was a little bear cub with a minimum die area and very low power consumption, and his name was Mishutka (MIPS M51xx, M62xx).
In short, MIPS 24K is the basis of the 32-bit section of the middle line of MIPS Technologies cores. They have 8 pipeline stages (which is more than 5 and less than 15), there is a transition predictor (unlike MIPS M51xx, M62xx), but there is no superscalarity (unlike MIPS I6400, P5600, P6600).
After MIPS 24K, MIPS 34K was added to which hardware supported multithreading was added. This is a rather elegant solution for the following problem.
The fact is that in recent decades, the speed of arithmetic calculations in the processor has grown faster than the speed of memory access:
In our era, when a cache misses data, the processor could execute dozens of arithmetic instructions. How to make the processor not idle (idle time of this type can take up to 50% of the typical program execution time)? That's how:
A couple of pictures from an article in The Microprocessor Report magazine:
Hardware support for multithreading on a single core should not be confused with multi-core. However, they may be present both individually and in combination. MIPS interAptiv (like its predecessor MIPS 1004K) is a multi-core system with a coherence manager for first-level caches (so that different modified data does not lie in L1 caches of different cores):
MIPS interAptiv is a modern optimized version of the line that started with MIPS 24K. That it is in the built-in computer MIPS Creator ci40. Although there are two processor cores in it, multi-core Linux treats them as four, since each of the two cores internally processes two streams of commands - hardware-supported multithreading. While one tread waits during cache miss, the other can work - this achieves greater CPU usage. Ultimately, this structure leads to energy savings compared to systems with a large number of single-threaded cores:
UPD: In the comments to the post an interesting question arose about registers with multithreading. I had to mention this on the slides.
Yes, in MIPS interAptiv there are several sets of registers visible to the programmer, which are switched for each thread. This causes the size of the processor to increase by about 20%. But the registers for the tail of the conveyor do not need to be switched, since by this moment the values of the operands have already been read.
Here is a document that describes everything that happens in each part of the MIPS 34K pipeline (in MIPS interAptiv, it is very similar):
https://imagination-technologies-cloudfront-assets.s3.amazonaws.com/documentation/MD00534-2B-34K-SUM-01.13.pdf
More documents from there:
https://imgtec.com/mips/classic
Oh, and do not forget to register for the webinar:
Source: https://habr.com/ru/post/310666/
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