ADM interface - what is “Tetrad”
The ADM interface is an internal standard of the Instrumental Systems company. It defines the rules for connecting the ADM submodules and base modules. The key element of the interface is the ADM FPGA. Initially used FPGA series FLEX10K and Acex 1K company Altera. In 2003, the transition to the Xilinx FPGA began. Almost all FPGA series from Spartan 2E to Kintex Ultrascale are used. The basic element of the FPGA project is the “tetrad”. This article is about that.
The basic version of the ADM interface on the basis of Altera FPGA is called “ADM Interface. Classic implementation. Its feature is the presence in the FPGA block of sixteen registers. Part of the registers served the FIFO, part of the registers was assigned to service the submodule. With the increasing complexity of the products of sixteen registers was not enough to organize management. The situation is complicated by the fact that on many basic modules only five or six address lines are connected to the FPGA, for more simply there are not enough legs. In such a situation, the logical solution is the organization of indirect addressing, but it requires that you leave quick access to the FIFO registers. As a result, a new implementation appeared, which was called the “ADM Interface. Progressive implementation.
The main element is the tetrad. A tetrad is a logical entity that has four directly addressable registers and 1024 indirectly addressable registers.
The logical organization of the tetrad is shown in the figure:
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Direct registers:
Indirectly addressed registers are divided into three groups.
The main feature of the command registers is that they can change their state either in the reset process or in the process of writing to the register. This allows the use of shadow RAM for reading from registers. And the use of shadow RAM allows sharply reducing FPGA resources to organize reverse reading from registers. Because of the shadow RAM, we had to enter a certain procedure for resetting the tetrad, it is required to form a reset signal and set the value 0 to all command registers.
The constant group stores the most important information about the tetrad. First of all, it is the tetrade identifier, the version number and the presence and direction of the FIFO. The tetrad identifier uniquely identifies the set of registers.
Direct registers allow registers to be implemented with any behavior, including additional status registers. It should be remembered that the implementation of the registers for reading will require the implementation of a multiplexer, which is a FPGA resource eater. It is recommended that the largest number of registers be placed in the command group and, by minimum, in the immediate group.
Currently, to organize the shadow RAM of all tetrads, only one FPGA memory block is used. This allows organizing 32 command registers and 32 constants in each tetrad. At any moment this quantity can be increased, but so far it has not been required.
In the FPGA firmware can be sixteen tetrads. Each tetrad controls its own complete part of the interface.
For example, the composition of the tetrads is given for the firmware of the FMC107P module and the submodule FM216x250MDA
The FPGA project is written in the VHDL language. To connect the tetrad, special data types are used, which dramatically reduces the amount of text. Currently, there are three types of connections. First of all, they differ in the width of the data bus, and in the second - in the type of connection signals.
Type 1 - 64-bit data bus width. Used with signal processors and PCI Express v1.1 x8 interface
Type 2 - 128-bit data bus width. Used with interface PCI Express v2.0 x8
Type 3 - data bus width 512 bits. Used with PCI Express v3.0 x16 interface
In all cases, the bus clock speeds up to 266 MHz. If you do not need maximum speed, it is recommended to reduce the clock frequency to facilitate tracing FPGA.
The base data type is bl_cmd
There is a separate type to describe the DMA request signal.
The description of the type 1 tetrad looks like this:
With the exception of clock and reset signals, six signals are used.
For a tetrad of type 2, the number of signals decreased to two.
As the FPGA grows in size, it becomes more difficult to place tetrad components inside the FPGA. This is due to the high clock frequency and long connections.
In this case, a high clock frequency is needed only for data transmission. To access registers enough 100 MHz. Connection types 1 and 2 use only one clock signal. Type 3 uses two clock frequencies and an additional component repack. The repack component is installed between the notebook and the bus connection. It has the parameter STAGE, which determines the number of additional triggers on the data bus. In addition, it is possible to implement several modifications for connecting type 1 and 2 notebooks. The figure shows the configuration in which the type 2 tetrad is connected through the REPACK_128 component and the type 3 tetrad is connected through the REPACK_512 component, using the parameter STAGE = 4 which allows you to set the tetrad in any location PLIS Virtex 7.
In conclusion, I would like to note that the tetrads turned out to be very convenient for modular construction of FPGA firmware and modular construction of software. The concept of tetrad is actively used for more than 12 years. The tetrads have experienced an increase in FPGAs and a change in series from Spartan 2E to Virtex 7 and are being introduced into the Ultrascale series. Input speed has risen from 200 MB / s to 11 GB / s. Supported by a large number of submodules. There was a transition from the internal standard ADM to the international standard FMC.
A more detailed description of the tetrads is given in the document: “DCR0340 - ADM Interface. Progressive implementation. In accordance with the rules of Habrahabr, I can not give a link to the document.
The basic version of the ADM interface on the basis of Altera FPGA is called “ADM Interface. Classic implementation. Its feature is the presence in the FPGA block of sixteen registers. Part of the registers served the FIFO, part of the registers was assigned to service the submodule. With the increasing complexity of the products of sixteen registers was not enough to organize management. The situation is complicated by the fact that on many basic modules only five or six address lines are connected to the FPGA, for more simply there are not enough legs. In such a situation, the logical solution is the organization of indirect addressing, but it requires that you leave quick access to the FIFO registers. As a result, a new implementation appeared, which was called the “ADM Interface. Progressive implementation.
Logical implementation
The main element is the tetrad. A tetrad is a logical entity that has four directly addressable registers and 1024 indirectly addressable registers.
The logical organization of the tetrad is shown in the figure:
')
Direct registers:
- STATUS - FIFO status register, contains FIFO flags
- DATA - FIFO data register
- IND_ADR - indirect address register
- IND_DATA - indirect data register
Indirectly addressed registers are divided into three groups.
- Group 1 - command registers, addresses from 0x000 to 0x0FF
- Group 2 - constants, addresses from 0x100 to 0x1FF
- Group 3 - immediate registers, addresses from 0x200 to 0x3FF
The main feature of the command registers is that they can change their state either in the reset process or in the process of writing to the register. This allows the use of shadow RAM for reading from registers. And the use of shadow RAM allows sharply reducing FPGA resources to organize reverse reading from registers. Because of the shadow RAM, we had to enter a certain procedure for resetting the tetrad, it is required to form a reset signal and set the value 0 to all command registers.
The constant group stores the most important information about the tetrad. First of all, it is the tetrade identifier, the version number and the presence and direction of the FIFO. The tetrad identifier uniquely identifies the set of registers.
Direct registers allow registers to be implemented with any behavior, including additional status registers. It should be remembered that the implementation of the registers for reading will require the implementation of a multiplexer, which is a FPGA resource eater. It is recommended that the largest number of registers be placed in the command group and, by minimum, in the immediate group.
Currently, to organize the shadow RAM of all tetrads, only one FPGA memory block is used. This allows organizing 32 command registers and 32 constants in each tetrad. At any moment this quantity can be increased, but so far it has not been required.
In the FPGA firmware can be sixteen tetrads. Each tetrad controls its own complete part of the interface.
For example, the composition of the tetrads is given for the firmware of the FMC107P module and the submodule FM216x250MDA
- TRD_MAIN - share management
- BPI_FLASH - access to bootable flash
- TRD_DDS9956 - control synthesizer
- PIOX_STD - digital port management
- TRD_FM216x250MDA_ADC - control ADC on submodule
- TRD_DDR3x - DDR memory management
- TRD_FM216x250MDA_DAC - DAC control on the submodule
Implementation on VHDL
The FPGA project is written in the VHDL language. To connect the tetrad, special data types are used, which dramatically reduces the amount of text. Currently, there are three types of connections. First of all, they differ in the width of the data bus, and in the second - in the type of connection signals.
Type 1 - 64-bit data bus width. Used with signal processors and PCI Express v1.1 x8 interface
Type 2 - 128-bit data bus width. Used with interface PCI Express v2.0 x8
Type 3 - data bus width 512 bits. Used with PCI Express v3.0 x16 interface
In all cases, the bus clock speeds up to 266 MHz. If you do not need maximum speed, it is recommended to reduce the clock frequency to facilitate tracing FPGA.
The base data type is bl_cmd
Type bl_cmd
type bl_cmd is record data_we : std_logic; -- 1 - DATA cmd_data_we : std_logic; -- 1 - CMD_DATA status_cs : std_logic; -- 0 - STATUS data_cs : std_logic; -- 0 - DATA cmd_data_cs : std_logic; -- 0 - CMD_DATA cmd_adr_we : std_logic; -- 1 - adr : std_logic_vector( 9 downto 0 ); -- data_oe : std_logic; -- 0 - DATA end record; There is a separate type to describe the DMA request signal.
Type bl_drq
type bl_drq is record en : std_logic; -- 1 - DMA req : std_logic; -- 1 - DMA ack : std_logic; -- 1 - DMA end record; The description of the type 1 tetrad looks like this:
component trd_user1 is port ( -- GLOBAL reset : in std_logic; -- 0 - clk : in std_logic; -- cmd_data_in : in std_logic_vector( 15 downto 0 ); -- CMD_DATA cmd : in bl_cmd; -- data_out : out std_logic_vector( 63 downto 0 ); -- DATA cmd_data_out : out std_logic_vector( 15 downto 0 ); -- bx_irq : out std_logic; -- 1 - bx_drq : out bl_drq; -- DMA …. ( ) end component; With the exception of clock and reset signals, six signals are used.
For a tetrad of type 2, the number of signals decreased to two.
component trd_user2 is port ( -- GLOBAL reset : in std_logic; -- 0 - clk : in std_logic; -- host2trd : in type_host2trd; -- trd2host : out type_trd2host -- …. ( ) end component; Type Definitions
type type_trd2host is record status : std_logic_vector( 15 downto 0 ); --! STATUS cmd_data : std_logic_vector( 15 downto 0 ); --! data : std_logic_vector( 127 downto 0 ); --! DATA drq : bl_drq; --! DMA irq : std_logic; --! fifo_rstp : std_logic; --! 1 - FIFO end record; type type_host2trd is record cmd : bl_cmd; --! cmd_data : std_logic_vector( 15 downto 0 ); -- data : std_logic_vector( 127 downto 0 ); -- 128 DATA end record; As the FPGA grows in size, it becomes more difficult to place tetrad components inside the FPGA. This is due to the high clock frequency and long connections.
In this case, a high clock frequency is needed only for data transmission. To access registers enough 100 MHz. Connection types 1 and 2 use only one clock signal. Type 3 uses two clock frequencies and an additional component repack. The repack component is installed between the notebook and the bus connection. It has the parameter STAGE, which determines the number of additional triggers on the data bus. In addition, it is possible to implement several modifications for connecting type 1 and 2 notebooks. The figure shows the configuration in which the type 2 tetrad is connected through the REPACK_128 component and the type 3 tetrad is connected through the REPACK_512 component, using the parameter STAGE = 4 which allows you to set the tetrad in any location PLIS Virtex 7.
In conclusion, I would like to note that the tetrads turned out to be very convenient for modular construction of FPGA firmware and modular construction of software. The concept of tetrad is actively used for more than 12 years. The tetrads have experienced an increase in FPGAs and a change in series from Spartan 2E to Virtex 7 and are being introduced into the Ultrascale series. Input speed has risen from 200 MB / s to 11 GB / s. Supported by a large number of submodules. There was a transition from the internal standard ADM to the international standard FMC.
A more detailed description of the tetrads is given in the document: “DCR0340 - ADM Interface. Progressive implementation. In accordance with the rules of Habrahabr, I can not give a link to the document.
Source: https://habr.com/ru/post/309136/
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