Compiler LLVM for MultiClet: WhetStone benchmark

In conversations about multicellular architecture , its applicability to a particular task in the context of the amount of natural parallelism present in it was often discussed earlier. Thus, when executing various benchmarks, in particular, CoreMark, we talked about the incompatibility of such programs with the multicellular architecture, due to the rather rigid sequence of the algorithm, which does not allow the cells within the group to extract a sufficient number of simultaneously executed commands. In this article, we will evaluate multiklets in more indicative conditions - using the WhetStone benchmark.


The WhetStone test differs in a favorable direction from CoreMark in the nature of the calculations carried out in it: all tests included in it, with the exception of the test speed of conditional transitions, have internal parallelism to one degree or another. Testing was performed in two versions. In the first, Multiclet R1, a compilation was made of the current version of the LLVM compiler with options:

-ffast-math -fno-builtin -O3 

In the second variant, the Multiclet R1 *, the testing was carried out with the introduction in manual mode of the prospective optimizations that are being added to the compiler now. Manual revision was to help the compiler increase the linear sections by combining several iterations of the cycle.
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results

System	MHz	MWIPS / MHz	MFLOPS1 / MHz	MFLOPS2 / MHz	MFLOPS3 / MHz	COS MOPS / MHz	EXP MOPS / MHz	FIXPT MOPS / MHz	IF MOPS / MHz	EQUAL MOPS / MHz
Multiclet R1 *	100	0.721	0.256	0.212	0.162	0.018	0.008	3.569	0.417	1.57
RPi 2 v7-A7	1000	0.585	0.28	0.291	0.248	0.011	0.006	1.314	1.209	0.981
RPi 3 v8-A53	1200	0.604	0.276	0.29	0.248	0.01	0.007	1.267	1.561	1.014
ARM v8-A53	1300	0.642	0.268	0.241	0.239	0.028	0.004	1.197	1.436	0.439
Core i7 4820K	3900	0.887	0.341	0.308	0.167	0.023	0.014	0.998	1.504	0.251
Core i7 1 CP	3066	0.873	0.325	0.295	0.174	0.025	0.013	0.892	0.958	0.167
Phenom II	3000	0.799	0.307	0.27	0.111	0.026	0.016	0.835	1.001	0.167
Athlon 64	2211	0.785	0.308	0.272	0.104	0.026	0.016	0.832	0.999	0.187
Turion 64 M	1900	0.884	0.302	0.258	0.145	0.026	0.016	0.827	0.988	0.187
Core i5 2467M	2300	0.853	0.296	0.298	0.163	0.022	0.013	0.807	0.993	0.222
Core 2 Duo 1 CP	2400	0.885	0.337	0.307	0.198	0.024	0.012	0.804	0.81	0.176
Celeron C2 M	2000	0.868	0.297	0.296	0.194	0.023	0.012	0.778	0.781	0.172
Core 2 duo m	1830	0.878	0.337	0.305	0.197	0.024	0.012	0.751	0.785	0.174
Multiclet R1	100	0.311	0.157	0.153	0.029	0.018	0.008	0.714	0.081	0.143
Celeron m	1295	0.832	0.324	0.297	0.178	0.022	0.012	0.631	0.923	0.173
Raspberry pi	1000	0.391	0.137	0.146	0.123	0.009	0.004	0.617	1.014	0.805
Athlon XP	2088	0.856	0.307	0.274	0.139	0.026	0.016	0.576	0.998	0.166
Pentium pro	200	0.79	0.332	0.278	0.146	0.023	0.013	0.575	0.755	0.149
Athlon4 barton	1800	0.846	0.305	0.272	0.137	0.026	0.016	0.571	0.988	0.165
Celeron a	450	0.76	0.291	0.276	0.14	0.022	0.012	0.569	0.751	0.147
Pentium 4E	3000	0.39	0.182	0.164	0.058	0.014	0.006	0.323	0.27	0.126
Atom m	1600	0.348	0.176	0.157	0.051	0.01	0.007	0.252	0.744	0.11
Pentium 4	1900	0.383	0.214	0.188	0.056	0.012	0.006	0.241	0.427	0.118
Pentium MMX	200	0.615	0.328	0.267	0.079	0.025	0.013	0.198	0.73	0.186
Pentium	100	0.604	0.322	0.267	0.078	0.025	0.013	0.192	0.568	0.183
80486DX2	66	0.182	0.076	0.068	0.026	0.008	0.005	0.105	0.212	0.017
* Option to use advanced optimizations compiler LLVM

It can be seen that in terms of MWIPS / MHz, multiklets look much more confident than in terms of CoreMark / MHz (figures published earlier in the article ). We can notice the following:

• The use of optimizations that increase the length of linear sections increases the overall MWIPS / MHz by approximately one and a half times.
• Such optimizations significantly expand the effective range of applicability of multicellular processors, due to the release of the previously hidden in the problem of internal parallelism.

The tests included in WhetStone can be divided into four groups. The first group includes tests for the performance of floating-point calculations. The results of these tests determine the indicators MFLOPS1 , MFLOPS2 , MFLOPS3 . It can be seen that the use of additional optimizations compiler LLVM gives a significant acceleration in all three tests.

Consider the nature of the resulting acceleration on the example of the MFLOPS1 indicator and investigate how such a result is achieved on the example of the first floating point arithmetic test. C test code:

 timea = dtime(); { for (ix=0; ix<xtra; ix++) { for(i=0; i<n1*n1mult; i+=5) { e1[0] = (e1[0] + e1[1] + e1[2] - e1[3]) * t; e1[1] = (e1[0] + e1[1] - e1[2] + e1[3]) * t; e1[2] = (e1[0] - e1[1] + e1[2] + e1[3]) * t; e1[3] = (-e1[0] + e1[1] + e1[2] + e1[3]) * t; } t = 1.0 - t; } t = t0; } timeb = dtime(); 

When compiling the test with an existing version of LLVM, we get the following assembly code for the body of the inner loop:

 jmp LBB2_4 SR4 := rdq #IR7, 2160 SR5 := rdq #IR7, 2152 SR6 := rdq #IR7, 2144 SR7 := rdq #IR7, 2136 SR8 := rdq #IR7, 2128 SR9 := rdq #IR7, 2120 SR10:= subf @SR6, @SR5 SR11:= subf @SR5, @SR6 SR12:= addf @SR5, @SR6 SR5 := addf @SR10, @SR4 SR10:= addf @SR11, @SR4 SR4 := addf @SR10, @SR7 SR7 := mulf @SR4, @SR8 SR10:= addf @SR5, @SR7 SR5 := subf @SR4, @SR10 SR11:= subf @SR10, @SR4 SR4 := mulf @SR10, @SR8 SR10:= mulf @SR5, @SR8 SR5 := addf @SR12, @SR10 SR10:= addf @SR11, @SR5 SR11:= mulf @SR5, @SR8 SR5 := mulf @SR10, @SR8 SR10:= addf @SR5, @SR6 SR5 := mulf @SR10, @SR8 wrq @SR9, #IR7, 2760 wrq @SR5, #IR7, 2752 wrq @SR11, #IR7, 2744 wrq @SR4, #IR7, 2736 wrq @SR7, #IR7, 2728 

It can be seen that many instructions in such a paragraph can be executed in parallel. However, combining several iterations into one allows you to significantly lengthen a section of code that is executed inside the intercellular environment without using memory, and also allows you to save time on saving intermediate results between iterations.


The second group of tests evaluates the speed of the basic mathematical functions and is characterized by COS MOPS and EQUAL MOPS indicators. Compiler optimizations do not have a noticeable effect on the performance of these tests, since the main burden rests on the mathematical library. The fact that the math library used was written under the old P1 processor and did not take advantage of many of the advantages of the newer R1 processor had a significant negative impact on the result of these tests.

In the third group of tests, you can combine the performance tests of integer arithmetic ( FIXPT MOPS indicator) and array performance ( EQUAL MOPS indicator). The tests of this group are affected by all the processes that improve performance in the first group, in addition, the increased linear sections obtained by combining loop iterations can be optimized using standard LLVM compiler optimization tools. These optimizations significantly reduce the number of intermediate calculations required and lead to the fact that the test totals for R1 are 1.5 ... 2 times higher than those of Intel and ARM.

The last group includes the performance test of conditional jumps with an IF MPS index. Low indicators of this test are due to a strict test sequence and, as a result, the lack of the required number of parallelism.

Thus, the current revision of the processor, with a sufficient length of the linear section and a sufficient number of mutually independent commands within it, provides execution speeds comparable to the current versions of the ARM and Intel family of cores. Good results are achieved for indicators MFLOPS1 , MFLOPS2 , MFLOPS3 . Excellent results on the FIXPT MOPS and EQUAL MOPS indicators are associated not only with the features of the multicellular architecture, but also with the results of compiler optimizations of the algorithm produced on the increased linear sections, which leads to some overestimation of the results in this test by reducing the number of actions performed. Not very good COS MOPS and EXP MOPS are determined by insufficient attention to the optimization of the mathematical library and will be improved in the future.

As for the compiler itself, then since the writing of the last article its functionality for the multicellular architecture has been significantly extended:

1. Added support for 64-bit integer arithmetic.
2. Added the ability to generate debug information.
3. Added target (option -target), which provides generation of assembler code only using real single-precision arithmetic (double, long double types are 32 bits in size, like float).
4. Added compiler options to ensure that only 32-bit write instructions are used (this was necessary due to the implementation of the external memory of the R1 processor, into which you can write only 32-bit values).
5. The library functions memset (), memcpy (), memmov () are optimally implemented.
6. Studies have been carried out on the possibility of compiler support for vector instructions, the results of which did not reveal the need to implement this possibility due to the limited set of vector instructions supported by the R1 processor itself.

In general, the LLVM compiler has been updated to version 3.8.1.