Junior FPGA Design Engineer: how to become?

• the list of topics that a novice developer should master under FPGA
• recommended literature for each topic
• a set of test questions and laboratory work
• classic novice bugs (and correction tips)

What you need to know and be able to

Digital circuit design

• know the basic digital nodes (logical elements AND / OR / NOT, encoders, multiplexers, totalizers, etc.)

• David Harris, Sarah Harris. Digital Design and Computer Architecture is a very large book, telling from the Azov to the top. There is a version in Russian . I looked through the Russian version: it is read very quickly and easily.
• Ugryumov E.P. “Digital circuitry” is a classic Soviet textbook, with all the ensuing consequences (some topics are explained too difficult, and you cannot immediately understand whether you need this information now or you can skip it). I read an older edition, perhaps in the 2010 edition, everything changed for the better, did not look.

1. What is the difference between digital circuitry and analog?
2. What are the basic digital nodes? In which of them the output depends only on the input?
3. What is a multiplexer? Draw a 4 in 1 multiplexer circuit from the primitive elements AND / OR / NOT.
4. Build a truth table for the expression: X = A or (B and C) or D.

HDL syntax

• knowledge of synthesized constructs (syntax) HDL-language
• knowledge of how to describe basic digital nodes using an HDL language
• understanding of what (on the part of basic digital nodes) this or that piece of HDL code turns into
• ability to write in HDL language to get the desired behavior

• Pong P. Chu. "FPGA prototyping by Verilog examples" - signs Verilog, starting with the basics. The syntax is detailed and there are a huge number of examples, both simple (counters) and higher levels (UART and VGA).
• Joseph Karshenboym. "Short course HDL" - a classic course in Russian.
• www.asic-world.com is a website with a bunch of examples on both Verilog and SystemVerilog.
• David Harris, Sarah Harris. Digital Design and Computer Architecture (see above)
• Stuart Sutherland. SystemVerilog for Design is a book about Verilog and SystemVerilog differences. Basic knowledge of Verilog is required to read. It is recommended to read to understand what amenities were introduced in the new standard.

1. How is blocking assignment different from non-blocking? When should one apply when another?
2. Is there a difference between the following three descriptions? If so, what is it manifested in?
   

   // code 1: assign a = b + c; // code 2: always @( b or c ) begin a = b + c; end // code 3: always @( * ) begin a = b + c; end 

 module test( input clk_i, input a_i, input [2:0] b_i, output reg x_o ); reg [7:0] cnt = 8'd0; reg [7:0] cnt2; wire c; reg d; always @( posedge clk_i ) cnt <= cnt + 1'd1; always @(*) begin cnt2 = cnt + 1'd1; end assign c = ( cnt < 8'd5 ) && ( a_i == 1'b0 ); always @( posedge clk_i ) begin d <= c; x_o <= c ? ( d ) : ( cnt2[ b_i ] ); end endmodule 

 module traffic_light( // c input clk_i, //   input rst_i, //  1,    ,  0 —     output red_o, output yellow_o, output green_o ); 

Simulation and verification of HDL-code

• know the non-synthesized designs of Verilog and SystemVerilog
• be able to write a simple testbench, run it in the simulator (for example, ModelSim)
• understand how the “perfect” testbench should be arranged

• testbench.in - a huge number of verification examples using Verilog'a and SystemVerilog'a.
• Chris Spear. “SystemVerilog for Verification” is a good, big book about verification using SystemVerilog. Reads easily, you can find answers to many questions.

• Altera. "Overview of Mentor Graphic's ModelSim Software"

1. How does function differ from task ?
2. Imagine that you wrote the simplest HDL model of a 5-stage RISC processor. How will you verify it? (The issue of increased complexity ).
3. What is the difference between a queue and a mailbox (data types in the SystemVerilog language)?
4. What is the difference between functional simulation and temporary one? When what should be used?

Fpga

• know what basic elements the FPGA consists of
• Understand how workflow development happens under FPGA
• Intuitively imagine which operations for FPGA are cheap and which are expensive (in terms of frequency and resources)

• Andrew Moore. “FPGAs for Dummies” is a story about FPGA in a very high-level (marketing) language. You can look with one eye.
• Altera Cyclone III Handbook - datasheet on the relatively old FPGA family from Altera.
• Steve Kilts. "Advanced FPGA Design" - a class book, reveals many nuances of development.

• Altera. Basics of Programmable Logic: FPGA Architecture
• David L. Jones (EEVblog). “What Is An FPGA?” Is a smart video with a story about what FPGA is.

1. What is the difference between FPGA and ASIC? What blocks does the FPGA consist of (or can it consist of)?
2. Try to outline the range of tasks for which it is good (economically feasible) to use FPGA, and for which MCU and CPU?
3. What hardware blocks do you know? What are they used for? (By hardware blocks we mean Hard IP ).
4. The Y family uses LUT with three inputs and one output. What is the minimum number of LUTs to calculate assign eq = (a == b); if a and b are 32-bit positive integers? And if LUT has four (five, six) inputs?
5. You need to create a single-port memory of 16 words. Each word is 100 bits wide. How many M9K blocks (9216 bits) will be occupied? We believe that we are doing a project under Cyclone III. (*)

Synchronous design and everything related to timings

• know the principle of synchronous design
• know the negative consequences of one or another scheme
• to have the concept of constrains

• Steve Kilts. “Advanced FPGA Design” (see above).
• Altera. The Quartus Handbook is the Recommended Design Practices chapter.
• Altera. Understanding Metastability
• nerudo. "Metastability trigger and inter-cycle synchronization"

1. What are timing constraints? Where are they described and what are they for (what are they used for)? What happens if you do not describe them?
2. What is clock domain crossing ? How and when should it be carried out?
3. What is the difference between synchronous and asynchronous reset? What will happen if a synchronous reset input has an asynchronous reset?
4. What is a latch (latch, latch)? What are the consequences of using latch? Give an example of the code that creates latch.
5. What is a combination loop? What are the consequences of using a combination loop?
6. What is metastability ? How to achieve it? What are its pros and cons?
7. What is a glitch? Do I need to deal with this? And if so, where and how?
8. What is setup time / hold time for a D-trigger?

CAD

• be able to create a project
• be able to describe I / O pins and constrains (at least for simple situations, without complex I / O interfaces)
• know what build reports there are, what information is contained in each of them
• be able to use the debugging tool on the hardware
• be able to use the tool for the analysis of timings ( STA )
• know what ready IP cores / modules (FIFO, RAM, FFT, DDR, Ethernet, etc.) the vendor provides and how you can add them to the project

• Altera. "Quartus Handbook"
• Altera. SignalTap II with Verilog Designs
• Denis Shehelev. “Synopsys Design Constraint - language for setting time constraints on the example of Altera TimeQuest” is a good series of articles in Russian. see also TimeQuest for Dummies .

• Altera. The Quartus Prime Software: Foundation.
• Altera. “Using the Quartus Prime Software: An Introduction”.
• Altera. "The Quartus II Software Interactive Tutorial".
• Altera. "TimeQuest Timing Analyzer"

1. What stages of assembly occur from clicking on the “Collect the project completely” button to get the finished binary file? What happens at each stage?
2. How to see if the CAD was able to put the project in the specified constraints (constraints)?

Lectures and laboratory

 : *   ?  . *   ( Quartus ).   Verilog: *      ( HDL ). * /  . *    : *      . * , /   *  . *     . *     . * /  . * . *   Verilog   . *     ( +SystemVerilog ): *    . . Testbench.    testbench. *    testbench'. *  .   . *     ( ,   .. ). *   tasks. *   . *      . * SystemVerilog Assertions. *  testbench    . *  c  (  ) . 

1. Introduction to FPGA.
2. Internal FPGA device.
3. Introduction to Verilog / SystemVerilog. Examples of the description of various types of logic.
4. Synchronous design. Create simple testbenches.
5. Description of FSM, arrays and structures in SystemVerilog. Memory: creation with Verilog and MegaWizard.
6. How DCFIFO works. Static Timing Analysis. TimeQuest, constraints.
7. Verification: coverage, assertions, SystemVerilog interfaces
8. Interfaces family Avalon. IP Cores. Qsys.
9. Verification: SystemVerilog OOP, constrained-random tests.

• Laba # 1.
• Laba # 2.
• Laba # 3.
• Laba # 4.

Classic mistakes

Confusion in assignments (blocking and non-blocking)

• you are not very confident about the question of blocking and non-blocking assignments (see above)
• you notice that you randomly change "=" to "<=" (and vice versa), hoping that it will work
• the simulator shows weird things, you start to doubt that you understand how the D-trigger works
• simulation results do not consistently coincide with what is happening on the gland (somewhere, something is floating in tact)

• Understand the Verilog material (see literature above)
• if you want the simulation result to coincide with what will be synthesized and embodied on the hardware, remember a simple rule: in blocks that describe combinational logic ( always_comb , always @ (*) ), you must use only blocking assignments ( = ). In the blocks that describe the triggers ( always_ff , always @ (posedge clk ...) ) you are obliged to use only non-blocking assignments ( <= ).

Timing problem

• simulation results do not match what is happening on the gland
• iron is unstable: sometimes clearly visible interference (for example, on VGA)
• "I added a signal tap, and after that the circuit stopped working correctly, I removed the signal tap and everything is fine"

• register all the necessary constraints (at least the used clock frequency (or frequencies) in the * .sdc file), connect this file to the project
• recompile the project. Go to TimeQuest and see if there are negative weak ones, and if there is, then further understand why this happens (perhaps it’s enough to twist the settings in Quartus, or you have to rewrite the pieces of code).

Not following the principles of synchronous design (asynchronous)

 // BAD EXAMPLE ... input clk_i, ... logic [7:0] sec_cnt; logic [7:0] min_cnt; logic last_sec_value; assign last_sec_value = ( sec_cnt == 8'd59 ); always_ff @( posedge clk_i ) if( last_sec_value ) sec_cnt <= 'd0; else sec_cnt <= sec_cnt + 1'd1; always_ff @( posedge last_sec_value ) min_cnt <= min_cnt + 1'd1; 

 // BAD EXAMPLE ... input clk_a_i, input clk_b_i, ... logic [7:0] cnt_a; logic [7:0] cnt_b; logic [7:0] sum; always_ff @( posedge clk_a_i ) cnt_a <= cnt_a + 1'd1; always_ff @( posedge clk_b_i ) cnt_b <= cnt_b + 1'd1; always_ff @( posedge clk_b_i ) sum <= cnt_a + cnt_b; 

• go through the whole project, write out (on a piece of paper) what clocking clock (signal) is used for each trigger.
• understand how this number can be reduced to the minimum number (within reasonable limits, of course), correct the code according to the rules of synchronous design.
• go through the whole project and carefully track how clock domain crossing happens (i.e. data transfer from one frequency to another). Correct if it happens incorrectly.
• perform all steps from the “Problem in Timings” .

Continuous debugging on hardware (ignoring simulation)

• edit hdl file
• complete project compilation
• flashing binary on board
• connection using SignalTap, viewing the desired signals
• understanding of the error, the transition to claim 1

• with SignalTap, you cannot see all the signals if you have a large project
• you take your time, or the time of your employer, when compiling a complete project, because this may take considerable time. On small chips, it takes 5-10 minutes, and you can type and score and go at this time to smoke / drink tea / play kicker, but on large projects this will go sideways.
• need a working board at hand
• you are not sure that the changes in the code are working and will not break something else

• write a testbench for the entire project, or for its parts
• achieve proper operation in the simulation
• build a project, check on the board

• walk on the points indicated above (timings and asynchronous)
• if there are no problems in timings, then try to understand at what input influences this happens
• submit these effects in the simulation, make sure that the problem is reproduced
• correct the error in the RTL code, check in the simulation and on the hardware
• Required : conclude why the previous version of the simulation could not catch this error

No development rules (+ code with backfill )

• You spend a lot of time reading (parsing) the code you wrote yesterday.
• You often write the same type of code (the most popular keys on your keyboard are Ctrl + C and Ctrl + V )
• you cannot understand the code that your colleague wrote (if you are working together on one module / IP core), and it is yours.

• Get acquainted with the literature that tells how to write good code, for example, McConnell. "Perfect Code"
• develop and describe the development rules for the team. Or use ready-made: NetFPGA , discussion on electronix # 1 , discussion on electronix # 2 , or one that I use.
• Give your review code to more experienced developers. You can ask about this on the electronix forum in the appropriate section. Of course, it is desirable that something more serious than the blinking of the LEDs, otherwise you just will not understand :).

Conclusion

• can easily answer the test questions above (without memorization, of course)
• decide correctly laboratory work
• get rid of the "classic mistakes"
• execute 1-2 projects on githab and check them on hardware. (preferably more complicated than blinking LEDs and watches).

Good day.
I am a student of 3 (4, 5) courses of such a university.
I like the idea of ​​writing under FPGA (concurrency, you can do what you want, blah blah blah) and like Java (made simple Android applications). I want to do something of this more or less seriously. What do you advise to teach?