Retrocomputing is different. Someone collects kilograms of ancient processors, someone restores Soviet EU EC computers, someone still disperses the Celeron in liquid nitrogen, and we enjoy the Altera University Programm Board UP1 of 1997 with the old CPLD MAX7128S and even blink a LED (and Not only).

Max, what is it?

Altera MAX (Multiple Array matriX) without numbers is a series of ancient CPLDs from Altera. This series was launched back in 1993 (more than 20 years ago!) And is no longer being produced; it has been completely replaced by the MAX II, MAX V and even MAX 10 series. At the same time, the MAX7000 was first released, then the “big” ones MAX9000, then "complex" MAX5000 and "cheap-low-voltage" MAX3000. Then added different letters S, E, B for JTAG, low-power and low-voltage versions, etc., in general, see the documentation.

We will be interested in the version of MAX7000S , which is distinguished by the presence of a JTAG port, that is, it implements the possibility of “programming in the system” through the built-in IEEStd interface. 1149.1 Joint Test Action Group (JTAG).

By the way, the first MAX7000 (without S) were programmed with a special hardware programmer and are practically not suitable for DIY.
')

Altera UP1

Altera chose a simple and unmistakable method to promote its product: in 1997 they announced the Altera University Program and began to distribute a debugging fee to (American) universities cheaply. The board was named Altera UP1 (from the University Programm). A little later, the second revision came out - Altera UP2, on which the wiring was slightly modified and the more capacious FLEX chip was soldered (about it just below).

Link from WebArchive about this board. (On the "parent" site has already been deleted.)

I must say that the idea of ​​the company Altera was a success. Dozens of universities have done laboratory work on this course on “High-speed Development of Digital Electronics”, etc. Googling on Altera UP1 and UP2 still gives a bunch of links, including even video courses.

One of the most comprehensive resources: users.ece.gatech.edu/~hamblen/ALTERA/altera.htm
More review: www.pyroelectro.com/tutorials/up2

The popularity of the board in the early 2000s was so high that even several books came out that mentioned this board (google Altera UP1 book), and the book " Rapid Prototyping of Digital Systems " by James O. Hamblen and Michael D. Furman was built entirely around this board, and can be considered as an extension of the documentation. (Those who wish will be found in two clicks). The book, by the way, has withstood several reprints, but since Edition 3 (SOPC Edition) it is based around the Terasic DEx boards, also loved by the pleisovods, but which do not fall under the retro prefix

Finally, in the 2010s, the fee was completely out of date, they began to be written off from universities and they began to appear on e-bay for ridiculous money, where, in fact, a couple of such cards were purchased. There is also a fly in the ointment - alas, students (even American ones) are not distinguished by accuracy, so broken I / O pins on such second-hand boards are not uncommon, and the CPLD recording resource is limited. So the chip may be slightly burnt, it is better to replace it immediately, since it is in the PLCC84 socket.

Deep googling gives a bunch of links to university resources of various countries, from Japan to Poland, which shows how much the board has spread. Whether the UP1 board was used so widely in Russia is not known for certain, but on the St. Petersburg LIAP website (forgive my old name), there was a textbook in Russian with a description of the board for some laboratory work. If someone else has used the board in other universities, let me know, it's interesting.

Now a few words about the board itself. In addition to the CPLD EPM7128S, the old FPGA FLEX 10K chip is also soldered on it, there is a DIP-8 panel for Configuration Memory, but for some reason the EPC1 chip is not included in the kit (maybe because it is disposable). The FLEX 10K chip is pretty decent even by modern standards, especially on the Altera UP2 - EPF10K70 board. As usual, there is a power stabilizer, two pairs of 7-segment indicators, quartz at 25.175 MHz, buttons, switches and just LEDs (you can blink!). VGA and PS / 2 sockets are connected to FLEX, you can even make video games, but this is not about FLEX.

The board comes with an old luxury LPT-shny JTAG Altera ByteBlasterMV (MV from MultiVolt). By the way, if you take it to e-bay, you must have ByteBlaster. True, why is it in the age of USB and in the absence of LPT - it is not clear, but there must be a complete set.

Warm 5 volts

Since the word “retrocomputing” was uttered, then yes, I must admit that attention to the MAX7000S was caused precisely in the aspect to apply it for integration into retro computers, for example, attach something for BK-0010 or Mikroshi. And the reason for the interest here is very simple: 5 volts TTL. It is clear that the era has changed and low-voltage progress cannot be stopped, but retro-and progress things, mmmm ... incompatible ...

One way or another, nowadays the 5-volt CPLD and FPGA have practically disappeared. The MAX7000S family is no longer recommended for use and is not being released, as is the competing Xilinx XC9500 series (without XL). The newer CPLDs are already “5-volt tolerant”, that is, at best, they do not burn at 5 volts input, but the output is still 3.3 volts, and on the 6502.org website there was information that some older processors do not work with 3.3 volt pins.

The MAX7000S can still be bought on e-bay / aliexpress not at a high price, but these are warehouse balances or, frankly, used chips. I once came a pretty scratched PLCC84 case, but then 6 pieces, although it was ordered 5. The Chinese, too, are well aware of what they are selling.

Programming with all the comforts

Courses on Altera UP1 recommend it to be programmed using the ancient program MAX + PLUS II, brutally draw diagrams from elements 2I-NOT and D-flip-flops and flash it with the Altera ByteBlaster programmer on the LPT port. This, of course, is great, but you should not confuse retro computing and masochism. Each plissovoda deployed Quartus II and has a USB Blaster. If not, then its prices have fallen so much that on aliexpress the USB-Blaster clone costs less than $ 5 and is undoubtedly recommended for purchase. Again, useful for DE2, etc. (Blasters are discussed below).

As for Quartus II, the latest version is 13.0 to support MAX7000S and the Web Edition is quite suitable. The functionality is slightly trimmed there, for example, the compiler does not support multi-core, etc., but this is not critical for us. The author generally deployed Quartus II 11.0 SP1 and everything works.

So, we will program in the modern VHDL, in the (almost) modern Quartus II and flash through the (almost) modern USB-Blaster. And all this on the retro MAX7000S. As they say, iron is retro, and software is comfortably.

There are plenty of CPLD / FPGA programming articles in the network, for example, on we.easyelectronics.ru in the FPGA hub, and there were almost a dozen on the dying Habré. Ideologically close, for example, is the Mars Rover project board , there is only a newer CPLD. So the Mars Rover tutorials will be quite useful to us.

The project is nothing special: let's make a 16-timer with display on 7-LED, since it is already soldered on the board. In addition, we will flash the decimal point. CPLD resources are very limited, there are only 128 macro cells in MAX7128S, so we will constantly check ourselves, looking at the resulting RTL and paying attention to the amount of resources expended.

First - you need to get a meander with a period of about a second, not necessarily exactly the same demo. We need a counter with a rather large conversion factor to divide 25.175MHz from quartz. We can divide, for example, by 2 ^ 24 = 16777216 and get a frequency of about 1.5 hertz. The classic synchronous counter +1 is not suitable here, because Quartus produces a giant adder for 24 bits, one input of which has a constant “1”. Tin. Let's make an ordinary divider from a chain of D-triggers, spending 24 cells, the so-called ripple-counter. A Grammar Design Nazis will say, this is a bad style, clock pulses must walk in global clocks, the counter must be synchronous, etc. To which we will answer simply - give us a PLL or do not need to put such high-frequency quartz.

To generate a long chain of triggers, we use the VHDL GENERATE construct. This is such a disguised macro operator of the VHDL language and you can do funny things with it, but everything is simple.


Top-level design is primitive extremely. Here we will make a classic counter for 8 digits, purely neighing to be terrified of the RTL implementation with an adder. But in real life everything is not so bad, the counter eats exactly 8 macrocells, but the adder is impressive, although it climbs into the standard logical part of the macrocells within the logic block. Compiler credit.


The 7-segment decoder does not cause problems and is synthesized into ordinary logic circuits with honest warm 5-volt pins for LEDs, although it eats a macrocell for each pin.


Result:

Do not forget to tie the weekend pins. For assignment, you can use the Pin Planner editor, but you can hardcore edit the text .QSF file. There is only one, perhaps, subtlety - the order of bits in the array, depending on the declaration of its TO or DOWNTO. Here you can see that the input goes to the DOWNTO side for compatibility with the counter bits (for the DOWNTO, the least significant bit is on the right) and the output to the 7-segment indicator is TO for compatibility with the documentation. You can also make it DOWNTO, but then you have to override the pin numbers.

Result: Logic cells; 47/128 (37%)

Firmware

The CPLD MAX7128S firmware doesn’t cause any problems; replacing the standard Altera ByteBlasterMV with the Altera USB Blaster runs quite smoothly, both in terms of the Quartus II and in terms of the Altera UP1 board. The JTAG connector has exactly the same pinout, and the pin VCC indicates the voltage of the JTAG port. Actually, therefore, ByteBlasterMV wore the prefix Multi Volt. The ability to work with different voltages USB Blaster inherited from ByteBlasterMV.

Altera Byte Blaster programmers and their clones have already been written in great detail.


The first two are almost standard Altera USB Blaster, and Terasic (or its clone, who can sort it out) seems to be licensed in general. As is well known, the “classic” USB Blaster is built according to the “FT245BM + CPLD + buffer” scheme as described in the manual .

The latter is a real Chinese miracle (more precisely, Japanese-Chinese). This is the FT245BM + CPLD emulator on the desperate PIC18F14K50. Nevertheless, Quartus II recognizes this “fake” as a native USB Blaster and the JTAG firmware function works. It is surprising that even the proprietary FTDI FT Prog finds a kind of FT245BM chip and reads something from it.

Here is a description of the insides of this Chinese clone emulator.

Conclusion

So, we were in the shoes of a student ~ 2007, while using VHDL and USB Blaster for CPLD firmware. The board is quite useful for entering the CPLD course, is a worthy competition to the CPLD and FPGA from LC Tech , which is loaded with aliexpress and is well worth buying if you see it is not expensive. Literature and courses on it a huge amount. The board works with standard TTL 5 volts and perfectly mates with old devices. Do not forget to only buy stock MAX7128S - a resource from them is not eternal.

In the next part, we will try to replace the MAX7128S with an Atmel ATF1508AS which is supposedly compatible and see what happens.