Digital filtering on FPGA - Part 1

Hello!

I have long wanted to start a series of articles on digital signal processing on FPGAs, but for various reasons I could not get down to this. Fortunately, there is some free time available, so from time to time I will publish materials that reflect various aspects related to DSP on the FPGA.

In these articles I will try to minimize the theoretical description of various algorithms and devote most of the material to the practical subtleties that I personally and my colleagues and acquaintances faced, one way or another connected with the development of FPGAs. I hope this series of articles will benefit both novice engineers and experienced developers.

Part 1: CIC Filter

In the first part, we consider the simplest CIC filter . CIC - “cascaded integral-comb”, in Russian - cascade integral-comb filter type IIR (with infinite impulse response). The class of such filters is widely used in tasks where work at several data transfer speeds is required. CIC filters are actively used for decimation and interpolation, that is, to reduce and increase the sampling rate. The CIC filter itself is nothing but a low pass filter (LPF). That is, such a filter passes the lower frequencies of the spectrum, chopping off the upper ones after the cutoff frequency. The frequency response of the filter is based on the law ~ sin (x) / x . The main advantage of CIC filters is that they do not require multiplication operations at all (unlike other types of filters, for example, FIR).
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Introduction

From the name you can guess that the base CIC filter is based on two basic blocks: an integrator and a comb filter (differentiator). The integrator (int) is a simple first-order IIR filter, made as the simplest battery. A comb filter is a first-order FIR filter.

Between the integrator and the comb filter, a node is often placed to increase or decrease the sampling frequency by an integer number of times - R.

In the case of lowering the sampling frequency, each R count is selected from the input sequence, forming a thinned output sequence.
In the case of an increase in the sampling frequency between the samples of the input sequence, zeroes are simply inserted, which are then smoothed in the integrating section, forming a sequence at an increased sampling rate.

Formulas for the transfer and amplitude-frequency characteristics are given below:

In more detail, with all the mathematical calculations about all aspects of decimation and interpolation, you can read in other sources, to which at the end of the article I will give links.

Decimator

If a CIC filter is used to lower the sampling rate, then it is called a decimator. In this case, the integrator is the first link, then the sampling rate decreases and, finally, the differentiating filter link goes.

Interpolator

If a CIC filter is used to increase the sampling rate, then it is called an interpolator. In this case, the differentiating link is in the first place, then the sampling rate is increased and, finally, the link of the integrating filter comes.

Depending on the delay of the input signal in the differentiating link, you can get different frequency characteristics of the filter. It is known that with an increase in the delay parameter D , the number of “zeros” of the amplitude-frequency characteristic (AFC) of the filter increases.

Note that for the integrator and comb filter (CIC filter), as the parameter D in the differentiating section increases, the frequency response zeros are shifted to the center — the cutoff frequency of the filter changes to Fc = 2 pi / D.

The cascade connection of the integrator and the comb filter without decimation and interpolation operations is called a “moving average” filter. The level of the first side lobe of such a filter is only -13 dB, which is small enough for serious DSP tasks.
Due to the linearity of mathematical operations occurring in the CIC filter, it is possible to cascade several filters in a row. This gives a proportional decrease in side-lobe level, but also increases the collapse of the main lobe of the spectrum (by spectrum I will often understand the frequency response of the filter). Thus, when the N- cascade connection of the same type of CIC filters is the multiplication of identical transfer characteristics. As a rule, sections of integrators and comb filters are combined together by type. For example, first sequentially put N sections of the same type of integrators, then N sections of the same type of differentiating filters.

The following figure shows the frequency response of the filter with different parameters of the sampling coefficient R (the calculation was made in MathCAD 14).

The frequency response of the CIC filter is fully equivalent to the frequency response of the FIR filter with a rectangular impulse response (IH). The total IM filter is defined as the convolution of all the impulse characteristics of the integrator and comb filter cascades. With increasing order of the CIC filter, its IM integrates the corresponding number of times. Thus, for the CIC filter of the first order, the EM is a rectangle, for the filter of the second order the EM is an isosceles triangle, for the third order the EM is a parabola, etc.

The increase in data width

Unfortunately, an increase in the delay value D in the comb structure and an increase in the order of the filter N lead to an increase in the transmission coefficient. This in turn leads to an increase in the bit width at the output of the filter. In DSP tasks where CIC filters are applied, one should always remember this and make sure that the transmitted signals do not go beyond the bit grid used. For example, the negative effect of the increase in the digit capacity is manifested in a significant increase in the used resources of the FPGA crystal.

Interpolator: the use of limited precision does not affect the internal digit capacity of registers, only the last output stage is scaled. A significant increase in data width occurs in integrator sections.

Decimator: The CIC filter decimator is very sensitive to the parameters D, R, and N, on which the capacity of the intermediate and output data depends. Both the differentiator and the integrator affect the final bit depth of the output signal.

In these formulas: B is the input data width, Bmax is the output data width, R is the sampling rate, D is the delay parameter, N is the filter order (number of stages).

Comment! The Hogenauer article describes the principles for choosing the width for each decimator cascade. When implementing their filters, Xilinx and Altera take into account the negative effect of the increase in the filter capacity and are struggling with this phenomenon using the methods described in the article.

Xilinx CIC Filter

Since I have 99% of my work related to Xilinx chips, I will give a description of the IP filter core for this vendor. But I dare to assure you that for Altera everything is almost the same.
In order to create a CIC filter, you need to go into the CORE Generator application and create a new project in which you specify the type of FPGA chip used and various other non-essential settings in this case.

CIC Compiler - Tab 1:

Component name is the name of the component (the Latin letters az, the numbers 0-9, and the symbol "_" are used).

Filter Specification:

Filter type - filter type: interpolating / decimator.
Number of stages - the number of cascades of integrators and comb filters: 3-6.
Differential delay - delay in differential filter cells: 1-2.
Number of channels - the number of independent channels: 1-16.

Sample Rate Change Specification:

Fixed / Programmable - type of discretization R: constant / programmable.
Fixed or Initial Rate - the value of the sampling rate R: 4..8192.
Minimum Rate - the minimum value of the sampling rate R: 4..8.
Maximum Rate - the maximum value of the sampling rate R: 8..8192.

Hardware Oversampling Specification: these parameters affect the output sampling rate, the number of ticks required for data processing. The level of parallelism inside the kernel and the amount of resources occupied also depend on these parameters.

Select format — select the frequency ratio of the filter: Frequency Specification / Sample period.
Frequency Specification - Frequency specification: the user sets the sampling rate and the frequency of data processing.
Sample period - Clock specification: the user sets the ratio of the processing frequency to the clock frequency of the data.
Input Sampling Frequency - input sampling rate: * .
Clock frequency - filter processing frequency: * .
Input Sampling period - the ratio of the processing frequency to the frequency of the input clock signal: * .

* - the range depends on the general settings and the sampling rate R.

CIC Compiler - Tab 2:

Numerical Precision:

Input Data Width - input data width: 2..20.
Quantization - output rounding: full accuracy / rounding of the discharge grid.
Output Data Width - the width of the output data, the range depends on the coefficients of N, D and R (the maximum value - 48 bits).

Optional:

Use Xtreme DSP Slice - use embedded DSP blocks to implement the filter.
Use Streaming Interface - use streaming interface for multichannel filter implementation.

Control Options:

ND - “New data”, the input signal that determines the flow of data to the input of the filter.
SCLR - synchronous filter reset (a logical unit at this input resets).
CE - “Clock Enable”, filter enable signal.

CIC Compiler - Tab 3:

Summary - this tab in the form of a list reflects the final settings of the filter (the number of stages, the frequency parameters, the width of the input, output and intermediate data, the delay in the filter, etc.).

On the left side of the CIC Compiler window there are three useful additional tabs:

IP-symbol - a schematic view of an IP block with active I / O ports.
Freq. response is the transfer characteristic of the CIC filter.
Resource estimate - estimated resources occupied.

After setting all the settings you need to click on the Generate button. As a result, after some time, the CORE Generator application will generate a whole set of files, of which we need the most basic ones:

* .VHD (or * .V ) - source file for modeling on VHDL or Verilog.
* .VHO - useless file, but from it you can take a description of the component and porting to insert into the project.
* .NGC - netlist file. It contains a description of the architecture of the IP core (used components and signal connections between them) for the selected FPGA chip.
* .XCO is a log file in which all parameters and settings of the IP core are stored. Useful file when working in Xilinx ISE Design Suite .

If you work in the ISE Design Suite environment, the CORE Generator will automatically create the necessary files in the working directory. For other development tools (such as Modelsim or Aldec Active-HDL), you need to transfer the necessary files to the appropriate working directory.

CIC Filter in MATLAB

Example 1: For simulation, a very convenient tool is the MATLAB program. For example, take the 4-order CIC filter model, made on logical elements from Xilinx System Generator Toolbox. Decimation and interpolation are not used (CIC degenerates into a moving average filter with a window of 16). Filter parameters: R = 1, N = 4, D = 16. The following figure shows the model of a single cascade in MATLAB.

Let's see what the impulse response looks like after each filter cascade. To do this, we apply a periodic single impulse to the system input.

It can be seen that the signal at the output of the first link forms a rectangular pulse of duration = D, at the output of the second link a triangular signal of duration 2D, at the output of the third link a parabolic pulse, at the output of the third a cubic parabola. The result is completely consistent with the theory.

Example 2: Directly the IP core of the CIC filter. Parameters: N = 3, R = 4, D = 1. The following figure shows the filter model.

If a single pulse with a duration of several cycles (for example, 32) is applied to the input of such a filter, then a parabolic-shaped signal is generated at the output, resembling a third-order moving average filter.

Summary

On this I would like to summarize. CIC filters are used in many tasks where you need to change the sampling rate. CIC filters are used in systems operating at several sampling rates (multirate processing), for example, in audio technology to change the bit rate (from 44.1 kHz to 48 kHz and vice versa). CIC filters are used in communication systems to implement DDC (digital down converter) and DUC (digital up converters). An example of using CIC filters: the AD6620 digital reception microcircuit from Analog Devices.

Implementing your own FPGA filter in HDL languages is often not required, and you can safely use ready-made kernels from vendors, or ready-made opensource projects. If you still need to implement your own CIC filter for an application, then you need to remember the following principles.

CIC filters have several features:

Simple to implement and do not require multiplication.
Decimation and interpolation on CIC filters is used everywhere to quickly change the sampling rate, both integer and fractional number of times.
With increasing order of the filter N and the magnitude of the delay D, the bit depth of the intermediate and output data increases.
With increasing order of the N filter, side lobe suppression increases and the main lobe of the frequency response increases.
It is recommended to use filters of the order of no more than 6-8, since with an increase in the order, the implementation becomes more complicated, the volume of occupied resources increases, and distortion of the frequency response of the filter within the passband occurs.
As the delay parameter D of the comb filter increases, the cutoff frequency of the filter changes, but for practical purposes, if the connection is cascaded, the parameter D <3.
When decimation R times significantly increases the bit at the output of the filter.
During interpolation, only integrating links make the main contribution to the bit depth of intermediate and output data.
The frequency response of the CIC filter is equivalent to the frequency response of the FIR filter with a rectangular impulse response. The total IM filter is defined as the convolution of all the impulse characteristics of the integrator and comb filter cascades.
When the frequency at the output of the filter in the FPGA is changed, the enable signal “clock enable” is used, and the processing frequency is not changed.
If the ratio "processing frequency / sampling frequency" >> 1, in the FPGA it is possible to reuse filter resources, thereby implementing processing with a minimum expenditure of crystal resources for a multi-channel system.
In modern CIC FPGAs, filters are implemented on DSP blocks (Xilinx, Altera), but in the absence of free resources, implementation on logical cells (SLICEs) is possible.
After the CIC filter, it is recommended to set a multiplier with a programmable gain (gain multiplier), which will adjust the signal level to the desired dynamic range.
CIC filters introduce distortion into the spectrum of the output signal, so after the CIC filter it is necessary to put a compensating FIR filter (the calculation method is presented in the Altera datasheet, MATLAB is required for the calculation).

Literature

To be continued...

Source: https://habr.com/ru/post/274845/

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