During the last three weeks, workshops on the processor at MIPSfpga FPGA were held at MIET, Moscow State University, MEPI, MIPT and other Russian universities. In the framework of the seminars, laboratory work was conducted on which it was demonstrated how to put MIPSfpga into practice
In the publication I will talk about my experiments with MIPSfpga, which are beyond the scope of laboratory work, I will consider the possibilities of integrating the MIPSfpga processor core with the opencores.org IP blocks. I will also tell you about porting MIPSfpga to some Altera FPGA-based boards (Fmax values ​​and FPGA resource utilization rates are given).

I want to make a reservation in advance that I am not in any way an experienced hardware developer on FPGAs, and began to master FPGAs specifically by working with MIPSfpga. Therefore, the presentation is conducted in a somewhat programming-centric manner.

Background: What is MIPSfpga

MIPS Technologies, the developer of the MIPS processor architecture, has a difficult fate: having started its work as an independent company in 1984, it managed to be part of Silicon Graphics (SGI), then regain its independence, and in early 2013 become part of Imagination Technologies, in which quality and remains at the time of this writing.
Processors with MIPS architecture are traditionally used to teach students microprocessor architecture, see, for example, the course of the MIPT-Intel laboratory .
MIPSfpga is a processor core with the MIPS32 architecture from the microAptiv family , specifically designed for training purposes. MIPSfpga is supplied as source code in Verilog language, which makes it suitable for FPGA synthesis. It should be noted that at the time of this writing, access to MIPSfpga can be obtained only by students and university professors.
MIPSfpga is not a toy at all, this processor core is not fundamentally different from the microAptiv processor cores that Imagination supplies on a commercial basis.
The microAptive family of cores, to which MIPSfpga belongs, can be attributed to the initial level, and although these cores are not aimed at achieving record-breaking performance, they are fully software compatible with more advanced cores. The MIPSfpga core complies with the MIPS32 release 3 architecture, incorporates MMU (TLB) and cache memory. If you wish, you can run linux on MIPSfpga.
Together with the original MIPSfpga, Imagination also offers a training manual which sets out examples of how to work with MIPSfpga.

mipsfpga-plus: system-on-chip for laboratory work

Laboratory work (and easier labs) on MIPSfpga in Russia was carried out by Imagination employee Yury Panchul. Yuri made tangible changes in the original materials of the works, primarily due to the fact that he had to adjust to the possibilities of the universities, in which labs were held.
For work, it is proposed to assemble a system-on-a-chip mipsfpga-plus which includes the MIPSfpga core and a small harness.
With some simplifications, the mipsfpga-plus structure looks like this:

In the figure, m14 is the MIPSfpga processor core (also known as the M14Kc core from the microAptiv family). For laboratory work, the interfaces that the kernel is connected to the outside world are important: EJTAG and AHB-Lite.
The EJTAG interface is a technological one and is designed for debugging programs running on a processor; for more information, see the EJTAG publication : an attraction for hackers .
But the AHB-Lite interface is essential for connecting the processor to the outside world. The AHB-Lite bus is a simplified version of the AHB bus, and in particular, AHB-Lite allows only one requestor ("master") on the bus. For details, refer to the document AMBA 3 AHB-Lite Protocol v1.0 Specification (ARM IHI 0033A).
mfp_ahb-light decoder & mux (hereinafter decoder ) is a block that decodes processor requests on the AHB-Lite bus and, depending on what address the processor addressed, redirects the request to one of the IP blocks:

• Ram;
• boot RAM;
• GPIO.

RAM is a block of memory for storing programs and data;
boot RAM - a memory block, completely analogous to the RAM block; the difference is that the boot RAM block contains a program that is executed immediately after the RESET signal is removed (since this block is mapped to the address 0x1fc00000).
The GPIO block consists of a series of registers, the digits of which are connected to the LEDs and buttons / switches on the board; a program running on the processor core can thus interact with the outside world.
For laboratory work, Yuri proposes to display individual m14 signals on board LEDs (such compounds are situational, and are not reflected in the figure).
Here is how the decoder maps the IP blocks to the physical addresses of the AHB-Lite bus:

IP block	Base address	Length
Ram	0x00000000	32K - 256K
GPIO	0x1f800000	0x14
boot ram	0x1fc00000	4K

Attention: on the AHB-Lite bus, the processor core issues a physical address , which, as a rule, does not coincide with the address that the program operates on ( program address or virtual address ). For more information about the intricacies of addressing in MIPS, see See MIPS Run , section Basic Address Space.

During laboratory work, the processor executes test programs, which can be loaded into the boot RAM in several ways.
The easiest option is to initialize the boot RAM at the stage of creating a bitstream for the FPGA. On the one hand, it is very simple - loaded the bitstream into the FPGA and the program starts to run. But on the other hand, if you want to make changes to the program, you will have to regenerate the bitstream, which can be quite expensive.
A more advanced way is to use the EJTAG debugging interface to download the program, but this method requires additional software and hardware — the JTAG adapter and openocd software (see the example of using EJTAG to load data into the Black Swift RAM: geektimes.ru/post/249184 ).
JTAG-adapter seemed to Yuri too exotic device, so especially for mipsfpga-plus in the Verilog language, he wrote an IP block implementing data loading in the S-record format via the UART interface (in the figure it is designated as uart_recv srec parser ). In this case, to download data to the boot RAM, it suffices to use an inexpensive USB-UART adapter and standard programs included in Linux or Windows. Immediately after switching on, the uart_recv block starts receiving data via the UART interface, while the processor core is stopped (the reset signal is active). After the end of data reception, the reset signal for the processor core is deactivated, and the uart_recv block is removed.
A more detailed description of mipsfpga-plus, see here .
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Porting MIPSfpga

Canon cards for MIPSfpga are Terasic DE2-115 and Digilent Nexys4 DDR.

However, there are reasons that led me to work on porting MIPSfpga to other cards.
For example, I simply could not buy a Digilent Nexys4 DDR board. This is what the site Digilent issued:
I received a negative answer to the request to Terraelectronics about the possibility to buy a board from them.
As for the Terasic DE2-115 board, in my opinion, its use for MIPSfpga is somewhat similar to shooting a gun on sparrows: the board has an FPGA with an excessive amount of resources for MIPSfpga, at the same time the cost of the board is quite high.
But the main thing is that porting the project to new boards will allow you to better understand how to work with FPGAs and expand the list of boards suitable for laboratory work!

Porting Criteria

For the sample, I conducted a synthesis of the reference project for the DE2-115 board:

Do not be confused by the fact that the project has eaten 3 Mbit of oncrystal memory - this value can be easily reduced. It is enough to reduce the size of the RAM and boot RAM blocks. To save on FPGA chip memory, there is even an opportunity to donate a part of the cache memory.
As can be seen from the report, about 15,500 logical elements (LE) are required from the FPGA. This means that it is necessary to focus on the FPGA with the number of LE more than 20,000.
We will try to find such cards.

Terasic boards

The Taiwanese company Terasic offers a wide range of Altera FPGA boards, and some boards purchased for training purposes can be purchased at a discount (Academic price):

Pay	DE0-Nano	DE0-CV	DE1-SoC
FPGA	EP4CE22	5CEBA4F23	5CSEMA5F31
family	Cyclone IV	Cyclone V	Cyclone V SoC
qty le	22K	49K	85K
memory, kbps	594	3080	4450
price	$ 79	$ 150	$ 249
Academic price	$ 61	$ 99	$ 175

Fee Mars Rover3

LLC "Inpro Plus" from Taganrog is the most interesting site marsohod.org , dedicated to the development of devices based on FPGA Altera. On the site, you can purchase the Mars Rover3, which is quite suitable for MIPSfpga.

The Mars Rover3 board has the MAX10 FPGA on 50000 LE with 1600 Kbit memory, and the cost of the board is 8000 rubles.

Connecting IP blocks with opencores

Labs in which it is proposed to look at what is happening inside the processor core are quite useful and instructive. However, it would be more interesting for me to assemble my system-on-chip on the basis of the present processor core from MIPS. This needs to be connected to the processor core by a number of peripheral devices. Interacting with the processor by pressing the buttons and looking at the LEDs is certainly good, but I want a more user-friendly interface. Almost all modern embedded systems use the UART interface for technological purposes, so I decided to add a UART to mipsfpga-plus.
Writing from scratch IP-block that implements the UART, was not my goal, so I decided to use ready-made. It is no secret that the most famous site with freely distributed IP blocks is opencores.org. And of course, there was an IP block that interests me. But the trouble is that for free-distributed IP blocks, the standard bus is Wishbone, which is not compatible with the AHB-Lite MIPSfpga bus.
I tried to connect the UART IP block through the AHB-Wishbone "adapter" , which is found on opencores.org; I was counting on such a connection:

In practice, it turned out that the adapter does not work, as I expected, so it turned out to be easier to modify the interface part of the UART IP block to support the AHB-Lite bus.
Since some software should work with the UART IP block, I borrowed the nmon nanomonitor from the barebox bootloader . nmon interacts with the user through the UART and has only basic capabilities: it allows you to write / print the word to the address, and also transfer control to the address.
However, nmon does not require RAM for its operation (sic!), Occupies less than 1200 bytes, works from any address in memory.
The small size allows you to put nmon in the boot RAM immediately during the synthesis. So now immediately after removing the reset signal on the UART interface, the nmon prompt is issued, and the user can either use nmon to load and run programs, or manually write / read in the address space of the processor, which can be useful during initial debugging of a custom IP block. Typical nmon session:

To connect another IP block to AHB-Lite, I had to manually edit the decoder block. Finally, the structure of mipsfpga-plus with the UART block connected is as follows:

The final project demonstrating the connection of the UART IP block with opencores to mipsfpga-plus is called myMIPSfpga. myMIPSfpga works on Terasic DE0-Nano, DE0-CV, DE1-SoC, as well as on the Mars Rover3.
The myMIPSfpga project is published on github: github.com/MIPSfpga/myMIPSfpga .

Use of Free Software

Although to generate a bitstream for the Altera FPGA, you have to use proprietary software Quartus (and there's nothing you can do about it), for many other tasks when working with MIPSfpga you can manage with free software.
To compile programs for MIPS, the gcc and binutils software is used (you can use the pre-assembled toolchain Sourcery CodeBench Lite 2015.05-18 , or you can build your own using crosstool-ng ).
To work with the MIPS processor for EJTAG, openocd and gdb are used. openocd can also be used to load bitstreams in the FPGA.
Icarus Verilog is quite suitable for modeling myMIPSfpga, and it is quite convenient to consider time diagrams from simulation results with GtkWave:

myMIPSfpga: use of FPGA resources

The workshop participants had questions about the indicators of the use of FPGA resources, as well as the Fmax values ​​for myMIPSfpga. Below, I present the obtained values ​​of the Slow 1200mV 85C Model Fmax Summary in MHz, with the values ​​for different versions of the Quartus II software:

Pay	FPGA	Quartus 13.1.4	Quartus 15.0.2
DE0-Nano	EP4CE22F17C6	31.66	31.22
DE0-CV	5CEBA4F23C7	31.24	34.06
DE1-SoC	5CSEMA5F31C6	28.24	37.17
Mars Rover	10M50SAE144C8GES	---	27.06

But indicators of the use of resources of different FPGAs:

Characteristic	Quartus 13.1.4	Quartus 15.0.2
EP4CE22F17C6
Total logic elements	15.342 / 22.320 (69%)	15.660 / 22.320 (70%)
Total combinational functions	14.161 / 22.320 (63%)	14.161 / 22.320 (63%)
Dedicated logic registers	7.665 / 22.320 (34%)	7.665 / 22.320 (34%)
Total registers	7665	7665
Total memory bits	95,872 / 608,256 (16%)	95,872 / 608,256 (16%)
5CEBA4F23C7
Logic utilization (in ALMs)	7.283 / 18.480 (39%)	6,972 / 18,480 (38%)
Total registers	7976	8127
Total block memory bits	95.872 / 3.153.920 (3%)	95.872 / 3.153.920 (3%)
5CSEMA5F31C6
Logic utilization (in ALMs)	7.264 / 32.070 (23%)	6.978 / 32.070 (22%)
Total registers	7951	8104
Total block memory bits	95,616 / 4,065,280 (2%)	95,616 / 4,065,280 (2%)
10M50SAE144C8GES
Total logic elements		37,206 / 49,760 (75%)
Total combinational functions		30,763 / 49,760 (62%)
Dedicated logic registers		25.165 / 49.760 (51%)
Total registers		25165
Total memory bits		78.464 / 1.677.312 (5%)

Note: Quartus 13.1.4 software does not support the MAX10 FPGA.

How could I use MIPSfpga with IP blocks with opencores

Support tools have been created for convenient work with the opencores.org IP blocks:

• fusesoc is a tool for controlling the system-on-chip assembly from separate IP blocks;
• wb_intercon - Wishbone switch generator.

fusesoc allows you to generate system-on-chip using high-level descriptions, while fusesoc will not only generate source code for Verilog, but also configuration files for Altera or Xilinx CAD systems.
wb_intercon allows you to generate a Wishbone switch code in Verilog; As input, a configuration file is used with parameters of Wishbone ports and switching rules.
According to the experience obtained when connecting the UART with the Wishbone bus to mipsfpga-plus, we can conclude that there will be a minimum of problems when building a system-on-a-chip from the opencores.org and MIPSfpga cores if the processor core itself connects to Wishbone immediately.
Suppose that we managed to make a normal adapter between AHB-Lite and Wishbone. Then a system-on-a-chip might look like this:

In the figure, the GPIO, UART, I2C, VGA, ETH, SPI, SDRAM5, HPC2FPGA blocks are real IP blocks from opencores.org, the connected Wishbone switch is used to connect them to the microprocessor core.

Note: of course the AHB-Lite-to-Wishbone adapter will introduce an additional delay; better performance can be achieved if Wishbone support is built into MIPSfpga. Moreover, following the example of the OpenRISC cores, you can display separate Wishbone buses for commands and data.

Afterword

Experience with MIPSfpga suggests that the initial development of the design of system-on-chip based on FPGA is not something complicated, costly and requires a long preparation. The availability of affordable FPGAs, free CAD systems, free software tools and manuals (I will especially note the site marsohod.org) allows you to master the FPGA design even at home.

Thanks

The author thanks the staff of Imagination Robert Owen and Yuri Panchula for the opportunity to work with MIPSfpga.
Special thanks to Nikolay Kovach and other authors of the site marsohod.org for the fees of the Mars Rover3, the EFO companies for the fees of Terasic DE1-SoC and Alexey Zhukov for the fees of DE0-Nano.
The author thanks the staff of NIISI RAS: Sergey Aryashev, Andrey Shcherbakov, Alexander Kornilenko and Andrey Arakelov for their help in developing CAD system Quartus II.
The author hopes that in the future the MIPSfpga license will be revised and this processor core will be available to all interested microprocessor architectures.