PCEPTPDPTE

From the translator. I present to your attention the translation of the post by Michael Steil (Michael Steil) http://www.pagetable.com/?p=308 . It touches upon the questionable practice of naming entities in the specifications of computational architectures.
This article very well reflects the situation with the names arising in the process of a long evolution of documentation, and my own perplexity when I first met with these concepts.
Comments to the text are available in tooltips.

And another entry in the page table .

I like Intel. I have already told how Intel tangled the x86 register nomenclature by expanding register A to AX (A extended - A extended), and then expanding the latter to EAX (extended A extended - extended A extended). Then AMD took and expanded the register again, giving it a more meaningful name: RAX.

I also explained earlier how Intel confused the naming of the x86 page table elements. The i386 has page tables ( PT , first level) and page directories ( PD , second level); Pentium Pro added page directory pointers ( PDP , level 3). Then AMD took and expanded the hierarchy again, giving the new element a more meaningful name: a fourth-level page map ( PML4 ).
')
With the advent of virtualization, both companies — Intel and AMD — added hardware support for nested page tables to eliminate the slow programmatic translation of shadow page tables; thus, the guest has 4 levels, and the host has four more.

AMD called this system a surprise! - nested page tables, NPT . Intel was more creative. With a history of architecture extensions , they reused the letter E: extended page table, EPT .

Let's practice. PD is a directory table, PDE is a directory entry (PD entry). It can also be called a PDPTE (a page directory pagetable entry) - the page directory in the page table, or second-level PTE, because, ultimately, all these entries at all levels of the hierarchy are PTE, because they have the same format. PDPPTE is a pointer entry to a directory in the page table, or a third level entry.

If we use nested pages, oh, sorry - extended pages - on an Intel system, then we will have to add the EPT prefix to all previous abbreviations. So, EPTPTE is a first level record, EPTPDPTE is a second level record, which should not be confused with EPTPDPPTE, which is on the third level; and at the fourth level we have EPTPML4PTE.

The next is better. Oracle / Sun / Innotek VirtualBox uses Hungarian notation for variable names, so “P” will be added for pointers, and “C” for constants. Now, what would you call a variable that stores a pointer to a constant — a second-level EPT record?

Of course, PCEPTPDPTE :

  / ** Pointer to const EPT Page Directory Pointer Entry.  * /
 typedef const EPTPDPTE * PCEPTPDPTE;

I thought about all this for a while, and thought even to patent my brilliant idea; however, here it is, not covered by a patent and free for all: Michael's nomenclature for Intel / AMD page tables:

New name	Description	Old name
P4	page 4 of the page table	PML4
P3	page 3 of the page table	PDP
P2	page 2 level of the page table	PD
P1	page 1 level page table	PT
P4E	record 4 levels of the page table	PML4E / PML4PTE
P3E	3 page table entry	PDPE / PDPPTE
P2E	entry level 2 page table	PDE / PDPTE
P1E	entry level 2 page table	PTE
NP4	page 4 levels of the nested page table	EPTPML4
NP3	page 3 levels of the nested page table	EPTPDP
NP2	page 2 levels of the nested page table	EPTPD
NP1	page 1 level nested page table	EPTPT
NP4E	record 4 levels nested page table	EPTPML4E / EPTPML4PTE
NP3E	entry 3 levels nested page table	EPTPDPE / EPTPDPPTE
NP2E	entry level 2 nested page table	EPTPDE / EPTPDPTE
NP1E	entry level 1 nested page table	EPTPTE

Use on health.