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Processor "in slow motion" and its system on a chip

Want to see how a slow motion industrial processor works? How do instructions roll from stage to pipeline, how do requests for reading from memory get past or miss the cache? What about building your system on a chip using the same microprocessor core used by Samsung engineers in the new Artik 1 platform? If so, this ad is for you:



Dear teacher of computer architecture, circuit design or system programming:
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The developer of microprocessor cores MIPS, the company Imagination Technologies, in collaboration with leading Russian universities and the manufacturer of microcontrollers Microchip Technology - announces a series of seminars in Russia devoted to the new product for education - MIPSfpga. Four free one-day seminars dedicated to MIPSfpga will be held from October 26 to 30 at the universities of Moscow, Zelenograd and St. Petersburg. In addition to them, MIPSfpga will be presented at a separate, paid seminar of Microchip Masters Russia in St. Petersburg / Zelenogorsk.

Site to register for MIPSfpga seminars at universities
bit.ly/mipsfpga-russia-registration

Site for registration for the Microchip Masters Russia seminar
bit.ly/microchip-masters-russia-registration

MIPSfpga - free licensed for university source code of industrial microprocessor core MIPS microAptiv UP. This core is used as the basis of the Microchip PIC32MZ microcontroller, as well as the new platform for the Internet of Things - Samsung Artik 1.

The MIPS microAptiv UP kernel is used in industry together with the chip design standard for the last 25 years, in which the processor and other components of the system on a chip are developed in the Verilog hardware description language, after which the description is transformed through several transformations into a mask microcircuits.

The educational version of MIPS microAptiv UP - MIPSfpga - uses an alternative implementation path: the system description turns into configuration files for inexpensive student cards with user-programmable gate arrays (FPGAs), often called programmable logic integrated circuits (FPGAs) or Field Programmable Gate Array (FPGA) .

This solution opens up many opportunities for education:

  1. Students can build their own prototypes of systems on a chip, connecting the microprocessor core, memory and their input-output devices
  2. Internal registers can be connected to output ports and output information about the current state of the processor pipeline, caches and memory management devices. After that, the processor can be started at a low clock frequency and observe its operation “in slow motion”.
  3. Students can experiment with their own variants of caches, design multi-core systems with specialized coprocessors, experiment with the division of the task into hardware and software.

Thus, MIPSfpga occupies a niche between the simplified academic implementations of MIPS, which are traditionally used in courses on micro-architecture - and finished industrial processors, in which students learn the programming of embedded systems. MIPSfpga is an ideal platform for teaching systems thinking at the intersection of hardware development and programming.

Venues and dates for MIPSfpga workshops, institutions and responsible instructors

Imagination Technologies Instructor - Yuri Panchul, Senior Equipment Development Engineer, MIPS Processors Division

October 26, 2015 - Moscow / Zelenograd , National Research University "Moscow Institute of Electronic Technology" ( MIET ). Instructors:


October 27 - Moscow , Moscow State University named after MV Lomonosov ( MSU ). Instructors:


October 28 - Moscow , National Research Nuclear University " MEPhI ", previously Moscow Engineering Physics Institute. Instructor:


October 29 - St. Petersburg / Zelenogorsk , Aquamarine Hotel, Microchip Masters Russia conference, organized by Gamma St. Petersburg , the official distributor of Microchip Technology in Russia.


October 30 - St. Petersburg , ITMO University , formerly St. Petersburg National Research University of Information Technologies, Mechanics and Optics. Instructors:



The contents of seminars at universities

  1. Greetings to the participants of the seminar.
  2. A short story about the educational programs of Imagination Technologies, a review of the processor cores developed by the company and their applications.
  3. A brief overview of the architecture (command system) of MIPS, the microarchitecture (pipeline device) of the MIPSfpga core and some of its blocks — caches and virtual memory management devices.
  4. Demonstration of a minimal system simulation with the MIPSfpga processor core using the Mentor ModelSim Student Edition simulator. Creating a project, simulation, loading a user program into the simulated system, analyzing the results on time diagrams.
  5. Demonstration of the synthesis, placement and tracing of the system with the core MIPSfpga in the environment of Xilinx Vivado. Creating a project, setting time constraints, using Xilinx IP blocks. Overview of the synthesized schemes at different stages, the interpretation of the report on timing and utilization of FPGA resources.
  6. Demonstration of loading the synthesized system into the FPGA configuration memory on the Digilent Nexys4 DDR board with the Xilinx Artix-7 FPGA.
  7. Demonstration of using the Codescape package for cross-compiling embedded programs written in C and assembler and converting them into formats suitable both for working in a simulated system, and for downloading to the FPGA system.
  8. Demonstration of connecting a cross-debugger running on a personal computer to the FPGA system using the BusBlaster debug adapter, OpenOCD package and the MIPSfpga core EJTAG interface.
  9. Discussion of porting MIPSfpga to boards with other FPGAs.
  10. Laboratory works in which seminar participants implement the simplest peripheral devices in Verilog, model the system on the ModelSim simulator, synthesize the system using Xilinx Vivado, load the result into the FPGA board, use the Codescape package to cross-compile programs and cross-debug to work with the system via debug adapter.
  11. Discussion of the use of MIPSfpga for a wide range of student labs, course projects and research in the field of heterogeneous systems on a chip.
  12. Conclusion, questions and answers.


check in

Participation in seminars at universities for employees of educational institutions is free, but the number of places is limited, so we ask you to register in advance.

Organizing universities provide computer classes for seminars, and Imagination Technologies provides FPGA cards, but if you can, we recommend bringing your own laptop with 64-bit Windows 7 or Windows 8, which has the latest version of Xilinx Vivado with a working license (free or paid) for RTL synthesis of Artix-7 FPGA. It is also advisable to pre-register in the Imagination educational program and download the MIPSfpga Getting Started and MIPSfpga Fundamentals packages. The installer for the Codescape Essentials package and the OpenOCD software for working with the BusBlaster debug adapter is located inside the MIPSfpga Getting Started package.

If you want to refresh knowledge of the basics of digital logic, concepts of hardware description languages, assembly concepts, architecture and microarchitecture processors before the seminar, we recommend that you download the free Russian translation of the popular textbook by David Harris and Sarah Harris “Digital circuit design and computer architecture” whose PDF file also available on Imagination Technologies' educational programs website.

We are waiting for you at the seminar!

Robert Owen,



University Programs Manager
Imagination Technologies
e-mail: Robert.Owen@imgtec.com
Web: community.imgtec.com/university

Source: https://habr.com/ru/post/265045/

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