Team sets should be free: the reasons for RISC-V

Translator's note. In the original article, the authors (one of them is the pioneer of RISC-processors D. Patterson) argue the need for the development of open ISA (instruction set architecture, processor instruction sets) and products based on them. Arguments are being made to stimulate the development of those areas of computing technology and economic niches in which commercial companies are not interested or are not flexible enough. They recall the successes of open standards and free software.

I came across an extended version of this article (as well as a counter article from ARM representatives and a counter-counter-paragraph from the authors!) In the August issue of the Microprocessor Report (MPR). Access to the MPR is limited and applies only to subscribers, but there is an original report in the public domain available on the website of the University of Berkeley. I also offer his translation below.

Instruction Sets Should Be Free: The Case For RISC-V by Krste Asanović and David A. Patterson. EECS Department, University of California, Berkeley - Technical Report No. UCB / EECS-2014-146 www.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-146.html
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Custom systems on a chip (SoC), in which processors and their caches occupy only a small part of the chip, become ubiquitous; Today it is already difficult to find an electronic device that does not use a processor as part of the SoC. Thus, more and more companies are designing chips that include processors than they did before. Given the revolution in open standards and open source software — for example, the TCP / IP network protocol and the Linux operating system — why is one of the most important interfaces remaining proprietary?

Arguments to support free, open ISA

Of course, some processor instruction sets (ISA, English instruction set architecture) can be proprietary for historical and commercial reasons. However, there is no solid technical basis for explaining the absence of free, open options.

1. This is not a mistake or omission. Companies that own successful ISA, such as ARM, IBM and Intel, own patents for the whims of their command systems, which prevents others from using them without licenses ¹ . Negotiations on the use last for 6-24 months and can cost from 1 to 10 million dollars, which excludes from the process academic organizations and all who require only small volumes of production ² . The ARM license does not even allow you to design your own kernel; you only get the right to use their design (only about 15 large companies have the right to create new ARM cores). Even “OpenPOWER” is an oxymoron; You must pay IBM to use this ISA. Reasonable with tz. business, this licensing practice stifles competition and innovation, preventing many from designing and sharing their own ISA-compatible cores.
2. This is not due to the fact that ISA owners themselves produce the overwhelming share of software for their systems. Despite the size of the software ecosystems that have grown around the popular ISA, the lion’s share of software for them is written by outsiders.
3. These companies do not possess the sacred knowledge required to create an adequate ISA. This is a lot of work, but many today can design a set of instructions.
4. Most popular ISA - not the most elegant. Both 80x86 and ARM are not considered good design standards.
5. Verification of compatibility with ISA does not require company controls. Open organizations have developed mechanisms for certifying hardware compatibility many years ago. Examples: IEEE 754 standard for floating point numbers, Ethernet, PCIe. If this were not the case, open IT standards would not be so popular.
6. Finally, there is no guarantee that proprietary ISA will exist for a long time. If a company goes bankrupt and disappears, it takes its ISA with it. The demise of DEC has completed the development of the Alpha and VAX instruction sets.

Note that ISA is actually an interface specification, but not its implementation. There are three approaches to implementing an interface:

1. Private closed, similar to Apple iOS.
2. Licensed open, like Wind River VxWorks.
3. Free and open, whose users can change and share, as is done in Linux.

Proprietary ISAs allow you to work with the first two approaches in practice, but you need a free, open ISA to support all three approaches.

From this, we conclude that the industry will benefit from a viable, freely accessible, open ISA to the same extent as it has been favorably impacted by the development of free open source software. For example, it will create a truly free open market for processor designs that are currently hampered by ISA fad patents.

This can lead to:

1. Innovation through competition in the free market of many designers, including open and closed ISA implementations.
2. The overall open design of the cores, which will be expressed in reducing the time to market for products, reducing the cost of reuse, fewer errors due to the attention of many people ³ , and transparency, which, for example, will make it difficult for government agencies to introduce secret backdoors.
3. Processors available for more devices, which will help develop the Internet of Things (IoT, Internet of Things), with a cost of the order of a dollar.

Arguments in support of RISC as a style for a free, open ISA

In order for an ISA to be accepted by the open source community, we believe that it should have a successful history of commercial use. The first question is: what style of ISA shows such a story? Over the past 30 years, history does not know of any successful stack architecture ( Translator's Note: a strange statement, given the success of Java bytecode and .NET CLI - stack architectures ). Except in the DSP (digital signal processing) segment of the application, VLIW also failed: Multiflow popped up, and Itanium, despite billions in investments from HP and Intel, did not receive recognition. For decades now, no new CISC ISA has been successful. The surviving CISC architectures transmit their complex instructions to simpler ISA, which is very justified for the execution of the valuable inherited code base. The new ISA, by definition, will not have such a base, so the additional expenses for equipment and power consumption required for broadcasting are difficult to justify: why not just use a simpler ISA? RISC -like load-store command sets have been known for at least 50 years, from the era of CDC 6600 by Seymur Kreus. While the 80x86 won the PC wars, RISC dominates the tablets and phones of the post-PC era. In 2013, more than 10 billion ARM were sold, compared to 0.3 billion x86. By repeating what we said in 1980 ⁴ , we believe that RISC is the best choice for a free and open ISA.

Moreover, the new RISC ISA can be better than its predecessors, if its development takes into account their mistakes:

1. The exception is too much: the absence of load / store commands for bytes and half words in the first Alpha ISA variant and the absence of load / store for floating-point numbers in MIPS I.
2. Inclusion of redundancy: built-in shift in ARM instructions and SPARC register windows.
3. The impact of micro-architectural details on ISA: deferred transitions in MIPS and SPARC, barriers-traps for floating-point numbers on Alpha.

To meet the needs of the embedded solutions market, RISC and even provided a solution to the problem of code size: ARM Thumb and MIPS16 added 16-bit formats so that the code was even shorter than that of 80x86. Thus, there is a generally accepted agreement on how a good RISC ISA should look overall.

Arguments for using existing free open RISC ISA

There are already three free and open RISC ISA ^5s :

• SPARC V8 - to Sun Microsystems honor, it made SPARC V8 an IEEE standard in 1994.
• OpenRISC is a GNU-licensed open-source project, launched in 2000, with 64-bit ISA completed in 2011.
• RISC-V - in 2010, partly because of the limitations of ARM on its IP and due to the lack of 64-bit modes, and also because of the general grotesque of ARM v7, we and our students Andrew Waterman and Yunsup Lee developed RISC-V ⁶ (pronounced "RISC-5") for the needs of our research and teaching activities and released it under the BSD license.

Since it usually takes years to polish all the subtleties — OpenRISC took 11 years to mature, and RISC-V took 4 years to complete — it would be better to start with an existing ISA, rather than form a committee and start from scratch. All RISCs are similar, so any one of them can be a good candidate.

Since ISA can exist for decades, it is necessary to first extrapolate and describe the future landscape of information technology in order to understand what features may be important to facilitate the prioritization process. Most likely, three platforms will prevail: IoT - billions of cheap devices with IP addresses and Internet access; 2) personal mobile devices, such as modern phones and tablets; 3) data centers (Warehouse-Scale Computers, WSCs). You can have different ISA for each type of platform, but life will be simpler if it is the same everywhere. This picture of the future offers four key requirements for it.

1. The format “basic ISA plus extensions” ⁷ . To increase efficiency and reduce costs, SoC-systems add their own application-specific accelerators. To do this, as well as to maintain a stable code base, a free, open ISA should have: a) a small core of instructions that are known to compilers and OS, b) standard, but optional extensions for frequent private SoC adaptation scripts to a specific application, c) space for Completely new instruction codes for accelerators.

2. Compact command encoding. A smaller amount of code is desirable because of the sensitivity of the price of IoT applications to the amount of memory used.

3. Quadruple precision (QP, quadruple-precision) of floating point numbers in addition to double and single precision. Some applications running in data centers today handle so much data that they already use software libraries for QP.

4. 128-bit addressing in addition to 32-bit and 64-bit. Memory restrictions of IoT devices mean that 32-bit addressing will be relevant for a long time. 64-bit addresses are the de facto standard for all large systems. Although the WSC industry will not require all ^2,128 bytes, it is likely that in a decade numbers greater than ^2,664 (16 exabytes) will be needed to address SSD storage. The limited size of the address space is one of those ISA errors that are difficult to fix ⁸ , it is wise to schedule large addresses now.

The following table summarizes the information about the three free open ISA on these four criteria, as well as on the presence of support by compilers and ported OS.

Arguments in support of RISC-V as a free open ISA

Our community must unite around a single ISA to verify that a free, open ISA can work in practice. Only RISC-V meets all four requirements. She is also 10 to 20 years younger than the rest of the RISCs, so we had the opportunity to analyze and correct their errors, such as SPARC and OpenRISC transition delay slots. Therefore, the RISC-V command system is simple and straightforward (see tables 4 and 5 of the original article, as well as www.riscv.org ). In addition to the fact that the rest of the ISA does not fulfill many of the requirements, there are questions to the fact that the 64-bit SPARC V9 is proprietary, and OpenRISC has lost momentum.
RISC-V still has a big boost. Table 1 lists the various groups designing SoCs based on RISC-V. Partly due to the use of a highly productive, open system for designing Chisel ⁹ equipment, Berkeley University already has 8 types of chips and new developments in the process. Table 2 shows that a single 64-bit RISC-V core occupies half the area, consumes half of the power and at the same time works faster than a 32-bit ARM with a similar pipeline or the same process technology. Although it is difficult to completely eliminate our bias in this matter, we believe that RISC-V is the best and safest choice for a free, open RISC ISA. Therefore, we will conduct a series of ¹⁰ seminars to expand the RISC-V community and, inspired by the examples from Table 3, plan to create a non-profit foundation for the task of certification implementations, as well as to support and develop ISA.

Conclusion

Our arguments are even clearer for an open ISA than for an open OS, since ISA changes very slowly, while algorithmic innovations and new applications require a continuous evolution of the OS. As well as TCP / IP, this is an interface standard that is easier to maintain and develop compared to the OS.

Open ISA has been used before, but they never became popular due to lack of demand for them. The low price and power consumption of IoT, the desire to have an alternative 80x86 for data centers, and the fact that the processor cores are only a small but ubiquitous part of all SoCs, combine into that offer that can satisfy the demand that has arisen. RISC-V is primarily aimed at SoC, with a basic set of never changing commands, given the long life of RISC ideas, with a slowly evolving subset of optional extensions, as well as unique instructions that will never be reused. Although the first bridgehead for RISC-V may be IoT or WSC, our goal is broader: just as Linux has become the standard OS for most computing devices, we see RISC-V as the standard ISA for all computing devices of the future.

Literature

1. Letter from MIPS (2002). brej.org/yellow_star/letter.pdf .
2. Demerjian, C. (2013). "A long look at how ARM licenses chips: Part 1 of 2," semiaccurate.com/2013/08/07/a-long-look-at-how-arm-licenses-chips
3. Raymond, E. (1999). The Cathedral and the Bazaar. Knowledge, Technology & Policy, 12 (3), 23-49 // Per. in Russian: Eric S. Raymond. Cathedral and Bazaar. lib.ru/LINUXGUIDE/bazar.txt
4. Patterson, D. & D. Ditzel. (1980) "The Case for the Reduced Instruction Set Computer." SIGARCH Computer Architecture News 8.6, 25-33.
5. We recently learned about the intentions of the Open Core Foundation about designing a 64-bit open core, based on SH-4, by 2016.
6. Waterman, A. et al. (2014). The ISA User Manual, Volume I: Version 2.0. EECS Technical Report No. UCB / EECS-2014-54, UC Berkeley.
7. Estrin, G. (1960) "Organization of computer systems: the fixed plus variable structure computer system." Western Joint IREAIEE-ACM Computer Conference, 33-40.
8. Bell, G., & W. Strecker. (1976) "Computer structures: What have we learned from the PDP-11?", 3rd ISCA, 1-14.
9. Bachrach, J., et al. (2012) "Chisel: constructing hardware in a Scalaembedded language." Proc. 49th DAC, 1216-1225.
10. The first RISC-V workshop will be held January 14-15, 2015 in Monterey, CA. www.regonline.com/riscvworkshop

Table 1. RISC-V projects outside the University of Berkeley (see the full table in the original report).



Table 2. Comparison of a 32-bit ARM (Cortex A5) with a 64-bit RISC-V core (Rocket) performed on a single process (TSMC 40GPLUS). Data taken from the ARM website and from the article by Y. Lee et al. "A 45nm 1.3GHz 16.7 Double-Precision GFLOPS / W RISC-V Processor with Vector Accelerators", which will be published in: the 40th European Solid-State Circuits Conference, September 22-24, 2014:



Table 3. Examples of open-source software funds that support and develop open-source projects for decades:



Tables 4 and 5. The format of the RISC-V instruction set. See in the original report.