Implementing the physical layer in switches

Almost all of our switches are declared as PHYless, this raises questions. What does this mean, what are the features, what should be considered?

For twisted pair range is available up to 100 meters, the optics can transfer from 300 meters using 10GBASE-SR to 80 kilometers using 10GBASE-ZR. The situation changes radically when the transition from external cables to printed circuit boards. Due to the huge density of signal lines, the range at which the signal maintains integrity is measured in inches.

To communicate with the switching fabric (ASIC), the SFP + ports use an electrical interface called SFI, and the transceivers are optimized to minimize size and power consumption; there is no place for supporting iron signal quality in them. Modern switching ASICs (for example, Broadcom Trident + and Intel Alta) are capable of receiving SFI signals directly from ports, and switches with this port implementation are called PHYless. However, if the length of the tracks does not allow to deliver the signal without distortion from the port to the matrix, an additional chip, called PHY or SERDES, is needed.
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What is he doing?


With a significant length of the tracks, the signal is distorted, one of the important functions of the chip is to compensate for this phenomenon, electronic dispersion compensation (EDC), which is necessary for 10GBASE-LRM and 10GBASE-ER to work. A number of other tasks are also performed:

1. Conversion of electrical interfaces (for example, SFI to XFI, or SFI to KR).
2. SERDES is a Serial / Parallel conversion (for example, one SFI line to four XAUI lines).
3. Signal integrity and re-timing recovery.
4. Physical layer functions, such as direct coding of the Physical Coding Sublayer (PCS).

Summary table of the capabilities of various types of physical layer implementations in switches:

	EDC PHY	Lite PHY	Retimer	PHYless
Clock Recovery (Retiming)	X	X	X
Equalizer	X	X	X
Singal conversion (ex. XLPPI / KR4 <-> XLAUI, XFI <-> SFI)	X	X
Auto Gain Control (Regeneration for amplitude control)	X
Microcontroller and DSP integrated	X
EDC for LRM	X
Roundtrip Latency (40nm, CMOS from BRCM)	50 ~ 70ns	5ns	<5ns	0ns
Power Consumption (40nm, COMS from BRCM)	500 ~ 700mw / 10G port	300mw / 10GE port	<300mw / 10GE port	0mw
Additional Features
IEEE 1588	X
Sync. Ethernet	X
MACSEC	X
Fcoe	X
Application	DSP based EDC PHY. Drive SFP +, QSFP + Modules and Backplanes. Supports 10GBASE-LRM / MACsec / 1588 / FCoE	Drive SFP +, QSFP + Modules and Backplanes	Simplex and Duplex Equalizers for Front / Backplane & Chip-2-Chip applications

Using the example of a switch with 48 ports 10G SFP + and 4 ports 40G QSFP + ( Eos 400 and similar with EDC PHY), we can deduce the advantages and disadvantages:

Benefits:

1. Reduced power consumption by 61W (240W-> 179W).
2. Reduced delays by 50-70ns.
3. Increase MTBF and decrease MTTR.
4. Significant price reduction

Disadvantages:

1. SFP-10G-LRM (Long Reach Multi-mode) is not supported.
2. You cannot implement the FCoE gateway (but it can work in the FCoE network).

If you do not need to build a network with distances between nodes over 10km, you do not need an FCoE gateway and accurate synchronization over the network, then the PHYless option is preferable. It costs less, consumes less, reliability is higher - what else do you need?

The vast majority of tasks fit under this framework :)