FPGA timing analysis or how I mastered Timequest

Good day, dear habravchane.

In fact, I am a radio physics engineer and programming an FPGA is not my direct activity, but at one point it took to write a program to synchronize several oscillographic modules. I had to master this science. About what problems I have with this, under the cut.



Many I hope at least one of you has programmed under the FPGA at a level higher than the blinking LED. If this was the case, then you might notice that sometimes something is wrong. There are problems with this kind of timings: as the frequency rises, the system becomes unstable, the bitics start to stick, the data disappears and the project does not work.
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This is a paraphrase of an article about where these problems come from and how to deal with them. The author of the post uses ALTERA and software for the development of the same company (Quartus II).

To better understand the essence of the problem, consider the simplest model of the 8-bit memory cell.

module habr111( input [7:0] data, input clk, output[7:0] out ); reg [7:0] count; always @ ( posedge clk ) count <= data; assign out = count; endmodule 

We start the simulator and see that when data comes to the input in a certain phase relative to the clock signal, garbage data appears at the output.



The fact is that the D-trigger digital device is only as a first approximation. That is, in essence, this is a set of analog transistors that have their own time of rising fronts. It happens that clock catches the moment when the signal grows to the voltage of the transition between 0 and 1. This is called a metastable state and what will be formed at the output is not obvious.

Also, each bit has its own delay: some bits arrive earlier, some later. If data switching occurs at the time of clock switching, then due to the effect described above, there is a mix of old and new bits to the output.

For the project to work correctly, you need to get rid of these effects. To do this, you must independently consider those times In Quartus II, this is the Timequest program. The question is: why do we need to know this?

The scheme by which timeqwest calculates timings consists of two registers. If all their parameters are known, she will calculate and do the correct wiring. But if there is some external register, about which Timequest has no information, then the developer needs to calculate and enter everything on his own. How this is done is described in this article.

My free translation .

I hope this will help someone as well as it helped me.