Intuitive description of the processor power states with the help of men and light bulbs

On any, even a complex topic, you can write interesting, intelligible and with humor. Intel engineer Taylor Kidd (Taylor Kidd), who regularly publishes articles on the energy saving states of Intel processors on the company's blog, has this talent. As a Friday positive, we suggest that you familiarize yourself with Taylor’s comic approach to a very serious problem. At the end of the post you will find links to other articles by this author.

This is another publication in a series of power management records for Xeon Phi co-processors. However, everything said here is true for any processor.
Apart from a hackneyed analogy with hares and turtles, I once mentioned "experienced programmers who diligently work on their corporate employers." Let's expand on this concept a bit. At KDPV we have one experienced programmer. It symbolizes one hardware CPU co-processor thread.
In the core - 4 hardware threads. Look at the picture below. Everything is so obvious that I will not bother writing, and you - reading a multi-page explanation. Also shown is a light bulb. The light bulb represents the core-supporting infrastructure, such as clock circuits and power circuits.


Experienced programmers in the room, i.e. the core of the Intel Xeon Phi co-processor

Power Management: C0 and C1 core

What does all this have to do with power management? Sometimes individual liberal arts students claim that engineers are devoid of imagination and generally bored. But we all know that even if some tediousness is sometimes alien to us, we cannot be blamed for lack of imagination. With this in mind, imagine that on each of these tables are computers and desk lamps.
The kernel in C0 mode: at least one experienced programmer is hard at work (that is, at least one hardware thread of the CPU core executes instructions).
The CPU executes the HALT instruction: when one of our experienced programmers finishes, it turns off its desk lamp, turns off the computer, and leaves (i.e., one of the hardware threads executes the HALT instruction).
After entering the C1 state: when all four experienced programmers finish their work, they all follow the HALT instructions. The last of them extinguishes the light in the room. (Ie, a decrease in the core clock frequency.)
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Power Management: C6 Core State

After entering the C6 core state: yes, I understand that this is obvious, but I like to talk to myself. Over time, everyone leaves for lunch. Since there is no one in the office, you can turn off even more electrical appliances (i.e., lower power consumption). However, remember that employees will return after dinner, so you need to be able to quickly turn everything off.


A building full of experienced programmers, i.e., Intel Xeon Phi co-processor

Power Management: Packet States AUTO-C3, DEEP-C3 and C6

Yes, this analogy could podnadoest you already, but I like it, so we continue.
Let's go a little further. Imagine a building with so many rooms, more than 60. Look at the picture above. Yes, I know that experienced programmers in Silicon Valley work in magnificent and spacious rooms, and not in close common offices. Unfortunately, this is where my analogy stops, because I just need an ordinary office.

Enter the state of the Auto-C3 package : everyone has left the floor, so the motion sensor automatically turns off the lighting on the floor. (Ie, coprocessor control software reduces the operating frequency of out-of-core components and other auxiliary elements of the chip.)
Entering the Deep-C3 package state is now a weekend, so air conditioning was turned off and telephone communication was turned off in the entire building (that is, in the MPSS coprocessor driver power management module). (Ie, the host lowers the voltage of the VccP coprocessor and forces it to ignore interrupts)
Entering the state of the C6 package : New Year holidays: the office is closed, all employees voluntarily or forcedly rest, so the office’s technical service turned off the electricity, air conditioning, telephones, servers, elevators, toilets, etc. (i.e., the host turned off the coprocessor power and turned off PCI Express traffic tracking *).

Power management: the further, the more wonderful

Inspired by our analogy, I decided to expand it to office building complexes (a node containing several co-processors), international engineering divisions (clusters in which each node contains several co-processors) and to attract external partners (distributed processing in the global network). However, common sense won, so I abandoned this plan.

Other Kidd articles (currently in English, but will soon appear in Russian - follow the column to the right):

• Intel Xeon Phi coprocessor Power Management Pt 0: Introduction and inquiring minds
• Intel Xeon Phi coprocessor Power Management Part 1: P-States Reducing power consumption without impacting performance
• Intel Xeon Phi coprocessor Power Management Part 2a: Core C-States, The Details
• Intel Xeon Phi coprocessor Power Management Part 2b: Package C-States, The Details
• C-States, P-States, where the heck are those T-States?