Achronix Plis - mastering experience

For more than a decade of working with FPGAs, I happened to work with products from four different manufacturers. With such a variety, one involuntarily draws attention to both the general features of the development process and the features inherent in a particular company. And so, a couple of months ago, I suddenly had the unique opportunity to get to know the new FPGA family, produced by a small but ambitious company from California. I'm talking now about the youngest FPGA manufacturer - the company Akroniks (Achronix) and the FPGA manufactured by it - Speedster22i HD1000.

Since its inception (2004), this young company has been able to develop HI-End FPGAs that have original architecture and unique characteristics. Moreover, the company was the first among all manufacturers of FPGAs to enter into a strategic alliance with Intel and since then has been producing its own chips (the size of which, as can be seen from the figure, has long gone beyond the “micro”) on the most advanced Intel-based technology in factories located directly to the USA. Now the Speedster series is released using 3D Tri-Gate 22nm technology. The development program of the series provides for the transition to 14nm and 10nm technical processes in the near future (as they are developed at Intel’s factories).

In this review article I want to briefly describe, on the one hand, those products that are used to work with Speedster FPGAs, and on the other, my experience (including emotions) of working with these products on the example of a very simple, but really completed project. So …
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Iron and development tools

Perhaps the only way to get familiar with the Speedster22i FPGA in use at this time is to buy (get a gift, rent, lease ...) the Speedster22i HD1000 Development Kit, which we did. In the process of waiting for delivery, preparatory work was done: a powerful computer with water-cooled, 32GB of RAM and two monitors was purchased. In order to get the development tools, I had to register on the Achronix website (http://www.achronix.com/company/contact-us.html) and get a user account. The user account provides access to the site zone, which contains the necessary software, as well as demo and reference designs. What is the difference between them? Reference designs come with source codes for the FPGA, while demo designs usually contain only FPGA boot files.

The registration confirmation took a couple of days and ended with the receipt of a letter containing the login and password. After that, it became possible to download the necessary tools to get started - Achronix's own shell called ACE and Synplify synthesizer. But in order for these programs to work, they still need license files. To do this, fill out another form and specify the MAC address of the network card. License files are sent by email. Their connection also did not cause any problems, in addition, this process is described in detail in the documentation. My computer is running Windows, but development tools are also available for Red Hat Linux.

The remaining time before the arrival of the board was devoted to studying the architecture of the Speedster22i HD1000 FPGA, mastering the design tools and writing a simple design.

What is interesting series Speedster22i? What distinguishes it from products of other companies? The Speedster22i FPGA has its own special feature - hardware-based IP cores focused on high-speed communication tasks. For the sets of such FPGA cores, Achronix is still out of competition. Nomenclature of cores: DDR-3 - 6 pcs., PCI Express Gen1 / 2/3 x1, x4, x8 - 2 pcs., Ethernet MAC up to 100G - 2 pcs., Interlaken - 2 pcs. This ensures a total bandwidth of over 400 Gb / s, which, of course, allows us to classify FPGA Speedster22i series to the category HI-END.

Otherwise, the FPGAs are not structurally different from those of other manufacturers: they consist of logical clusters (based on 4-input LUTs), block and distributed memory, as well as arithmetic units including powerful 56-bit multipliers. All this is available in sufficient quantities to achieve the most complex functionality. The speed characteristics are also impressive: the memory, for example, has a maximum operating frequency of 750 MHz. The main characteristics of Speedster22i FPGA are given in the table below:

Options	HD680	HD1000	HD1500
Logic volume, including hardware controllers (effective LUT cells)	660000	1045000	1725000
Programmable Logic Volume (in LUT)	400,000	700,000	1,100,000
Number of BRAM modules	600	1026	1728
Number of LRAM modules	4320	6156	10368
The amount of 80 kilobit BRAM (total Kbit)	48000	82080	138240
Volume of 640-bit LRAM (Kbit total)	2765	3940	6636
Multipliers (28 × 28)	240	756	864
The number of lines SerDes 12.75 GB / s (gigabit / s)	40	64	48
The number of lines SerDes 28 GB / s (gigabit / s)	-	-	sixteen
Ethernet hardware controllers (MAC level) 10/40/100 Gigabit / s	2	2	four
Interlaken LLC Controllers	one	2	four
PCI Express Controllers LLC	one	2	2
DDR2 / DDR3 Controllers	four	6	6
PLL number	sixteen	sixteen	sixteen
Number of Leads, Chassis FBGA2601 52.5 × 52.5 (12G, 28G, GPIO)	-	64,0,960	48.16.960
Number of pins, chassis FBGA1936 45 × 45 (12G, 28G, GPIO)	40,0,684	40,0,684	20,4,684
Number of pins, chassis FBGA1520 40 × 40 (12G, 28G, GPIO)	18,0,684	-	-

The minimum required set of development tools includes two programs - the ACE shell and the Synplify synthesizer. The company's own development - the ACE shell includes the means of placement and wiring, kernel configuration, loading and debugging. As a synthesizer used Synplify program from Synopsys. The approach of using a set of separate programs instead of a single integrated environment is typical for small companies. It is less convenient for novice developers, but for experienced engineers it gives greater flexibility and better quality of implementation of each stage. If a deeper integration is needed, all the required software can be combined, for example, using the HDL-designer shell from MentorGraphics.

To these programs, it is desirable to add any simulator. The Achronix package contains libraries for the most popular simulators, but these programs themselves are not included in the package and must be purchased separately.

And now, finally, the long-awaited fee arrived at our office!

Hands trembling with excitement (and how not to worry when the price of the board is like an inexpensive imported crossover!), The board was unpacked, transferred to its “regular” place - on an antistatic mat on my desktop and examined with interest.

As you can see, the board itself is a complex and multifunctional product. The circuitry alone takes up 90 pages! Therefore, it is not surprising that the board allows developing and debugging, I’m not afraid of this word, unique projects, for example, creating equipment for Ethernet 100G networks, for which there is a connector for the CFP module (“black square” in the lower left corner in the photo above). Two Interlaken interfaces are routed to the AirMax connectors.

Most struck by the thickness of the PCB. How many layers are there? 20? thirty? 40? The question remained unexplained.

The board has a PCI-express connector (Gen 3 x8, 64 Gb / s) and can work as a peripheral device as part of a computer. Together, it looks like this:

The package includes a JTAG cable that acts as a bootloader and debugger. A feature of this cable is the ability to work via USB-port, or via Ethernet. In the latter case, you can organize remote access to the device. When working via Ethernet, an external power supply is required (included in the delivery). Also included are a powerful power supply for the board itself and a 2GB DDR-3 RAM module.

Health check

Check that the board functions turned out to be very simple, because the ACE shell is already built in for it. Therefore, the whole test, in fact, comes down to pressing a single button to load test firmware. After that, you can play with the switches by turning the LEDs on and off and test the internal memory blocks. The board must be connected with a USB cable to the computer.

Development

And now - how I was doing my first project for Achronix FPGA. As such, the simplest option was chosen - a counter with the output of the higher digits on the LEDs. Of course, such a simple project will not impress professionals, but it allows you to explore the basic functionality of the development tools used to work with Achronix FPGAs and to master the design route. In future publications, I plan to talk about more complex things, such as configuring and using hardware cores and implementing systems on a chip using the ARM processor core.

Project structure

I place each project in a separate directory containing at least 3 subdirectories:

Src - for source code
Syn - for synthesis
TR - for implementation

Practice has shown that it is better not to keep anything in the Syn directory, because the synthesizer can overwrite the files placed there. Therefore, the source code (I prefer to work in Verilog) is stored in the Src directory, and all scripts are stored in the TR directory.

Source texts

The source code of the module is completely uncomplicated:

module counter #( parameter CNT_WIDTH = 32 ) // 8 <= CNT_WIDTH ( input wire clk, input wire rstn, output wire [7:0] leds ); wire rst; reg [CNT_WIDTH-1:0] cnt; assign rst = ~rstn; always @(posedge clk or posedge rst) if (rst) cnt <= 'h0; else cnt <= cnt+1; assign leds[7:0] = cnt[CNT_WIDTH-1: CNT_WIDTH-8]; endmodule

But for implementation on a demo board, it needs to be slightly modified.
First, you must select and properly connect the clock source. There are several of them on the board. After studying the source was selected with a frequency of 100 MHz, having a differential output. Consequently, it was necessary to add a differential buffer to the input clock circuit.

Secondly, I would like to see the internal signals in the process. All manufacturers of the FPGA have such an opportunity, it is also available in the Achronix FPGA. The internal signal analyzer is called SnapShot. Unlike competitors, the SnapShot component must be explicitly described in the design. This at first caused me inconvenience, but then I appreciated the advantage of this approach. This advantage is in complete control over what you do. In addition, this approach allows very flexible configuration of triggers for registering tracked events.

So, in the final version, we have a differential clock input and a buffer for it, as well as the ShapShot component for studying internal signals. Verilog final text:

 `define USE_SNAPSHOT module counter #( parameter CNT_WIDTH = 30 ) // 8 <= CNT_WIDTH <= MNTR_WIDTH ( `ifdef USE_SNAPSHOT input wire tck, input wire trstn, input wire tms, input wire tdi, output wire tdo, `endif input wire clk_p, input wire clk_n, input wire rstn, output wire [7:0] leds ); //********************************************** wire clk; wire rst; reg [CNT_WIDTH-1:0] cnt; assign rst = ~rstn; IPAD_DIFF #( .odt("on"), .termination("100") ) synth_clk_pad ( .pad(clk_p), .padn(clk_n), .dout(clk) ); always @(posedge clk or posedge rst) if (rst) cnt <= 'h0; else cnt <= cnt+1; assign leds[7:0] = cnt[CNT_WIDTH-1: CNT_WIDTH-8]; //********************************************* `ifdef USE_SNAPSHOT localparam MNTR_WIDTH = 36; wire [MNTR_WIDTH: 0] ss_zeroes; ///// Signals going to trigger-detector block to do pattern matching wire ss_clk; wire [MNTR_WIDTH-1 :0] ss_monitor_ch; /// Signals monitored in Snapshot wire [MNTR_WIDTH-1: 0] ss_trigger_ch; ///// Signals going to trigger-detector block to do pattern matching wire ss_rstn_out; ///// Active low user reset signal. wire ss_Arm; ///// Indicates Snapshot activity. wire [MNTR_WIDTH-1:0] ss_Stimuli; ///// User specified values for 3rd trigger pattern value assign ss_clk = clk; assign ss_zeroes = {MNTR_WIDTH+1{1'b0}}; //// //////// Now Snapshot macro block instantiation /////// ACX_SNAPSHOT #(.MNTR_WIDTH(MNTR_WIDTH) ) snapshot_0 ( .tck ( tck ), .tms ( tms ), .trstn ( trstn ), .tdi ( tdi ), .tdo ( tdo ), .usr_clk ( ss_clk ), .Monitor_ch ( ss_monitor_ch ), .trigger_ch ( ss_trigger_ch ), .Rstn_out ( ss_rstn_out ), .Arm ( ss_Arm ), .Stimuli ( ss_Stimuli ) ); assign ss_monitor_ch = { ss_zeroes[MNTR_WIDTH-1: CNT_WIDTH], cnt[CNT_WIDTH-1:0] }; assign ss_trigger_ch = ss_monitor_ch; `endif //********************************************** endmodule

Synthesis

To work with Synplify, apart from the source texts and links to the element library, the constraint file is required (usually it has the .sdc extension). Although it is optional for such a simple design, it is better to specify it. In such a simple case, like ours, you only need to specify the names of the clock signal and their parameters.

 # synplify_constraints.sdc set_hierarchy_separator {/} create_clock clk_p -period 10 create_clock tck -period 40 set_clock_groups -asynchronous -group { tck } -group { clk_p }

Next, create a project for Synplify, specify the files and libraries required for the synthesis, and start the process. If everything is done correctly, we get the output file with the extension .vma. (The “gurus” of an FPGA design may indicate that the main output format of Synplify is edif. But ACE accepts only verilog netlists that just have the .vma extension) as input.)

Implementation

The implementation process itself is carried out according to the standard scheme:

Create a project for ACE
Specify the synthesis results file in the project (with the extension .vma)
Set the constraints
We start the implementation process
We receive the file for loading in FPGA

For the implementation, it is necessary to prepare two files of the constraints: for defining clocks and defining pins. Their contents are shown in the table:

 # Ace_constraints.pdc create_clock clk_p -period 10 create_clock tck -period 40 set_clock_groups -asynchronous -group { tck } -group { clk_p } # io_preplacement.pdc set_placement -batch -fixed {p:clk_p} {b:P19} set_placement -batch -fixed {p:clk_n} {b:P18} set_placement -batch -fixed {p:rstn} {b:P17} set_placement -batch -fixed {p:leds[0]} {b:AE47} set_placement -batch -fixed {p:leds[1]} {b:AJ46} set_placement -batch -fixed {p:leds[2]} {b:AC46} set_placement -batch -fixed {p:leds[3]} {b:AF47} set_placement -batch -fixed {p:leds[4]} {b:AF46} set_placement -batch -fixed {p:leds[5]} {b:AJ47} set_placement -batch -fixed {p:leds[6]} {b:AG46} set_placement -batch -fixed {p:leds[7]} {b:AE46}

On the computer, the implementation phase is as follows:

Design loading and debugging

To download the firmware file created in the previous step, go to the “Download” window, click on the “Run 'Program” button and wait a couple of minutes.

When the FPGA is finished loading, it immediately starts working and we can observe on the board a line of fun flashing LEDs.

To view the internal signals connected to the SnapShot module, you need to open the “Snapshot debugger” window. In this window, you can configure trigger capture modes and other parameters. The analysis is started with the “Arm” button, after which the tracking of the trigger state begins. After installing the trigger, a time diagram of the recorded signals appears on the screen (with a slight delay).

Conclusion and conclusions

In a short time, Achronix managed to create interesting, competitive HI-END FPGAs and development tools for them. The technology of working with them will not cause problems even among mid-level specialists. Achronix products are already available in Russia.