Java Multicore Programming: Lecture # 1

Good day.
On May 15, the first webinar (out of 16) of the course "Multicore programming in Java" was held . Here I would like to publish the materials mentioned in the lecture: links to sources , terms , pictures , task . Perhaps someone will find them useful.

I also teach Scala for Java Developers on the udemy.com online education platform (equivalent to Coursera / EdX).

Introduction

• Moore's Law , Moore's law
• Herb Satter, “The Free Lunch Is Over”
• Amdahl's Law , Amdahl's law

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"Iron"

It is necessary to "see pictures" in the following sources

• "What Every Programmer Should Know About Memory"
• "The Architecture of the Nehalem Processor and the Nehalem-EP SMP Platforms"
• "A Primer on Memory Consistency and Cache Coherence"

Textbooks

Maurice Herlihy, Nir Shavit, “The Art of Multiprocessor Programming” : “Hardware Basics” page 469-482

"Pictures"

Memory hierarchy # 1


Memory hierarchy # 2


Memory hierarchy # 3


Typical time to access different memory levels


Examples of registers specific processor


Schematic interaction of cache controllers


False sharing: code


False sharing: effect (negative scalability)


Poor consistency between cores, caches, and data.


Good correspondence between cores, caches and data.

Terms

Terms
CPU, core, multicore era, memory wall, memory hierarchy, registers, L1 / L2 / L3 caches, cache line, false sharing, memory padding, cache pollution, cache miss, SMP, NUMA, multisocket, thread affinity

What to read in terms
- Mechanical Sympathy: "CPU Cache Flushing Fallacy"
- Mechanical Sympathy: "Memory Access Patterns Are Important"
- Mechanical Sympathy: "False Sharing"
- Mechanical Sympathy: "False Sharing && Java 7"
- Ruslan Cheremin: “False sharing”
- Ruslan Cheremin: “Cache coherency # 3: false sharing”
- Ruslan Cheremin: “How caching affects hashing”

Assignment to Lecture # 1

Write a utilitarian class (in variant A or in both variants (A and B)), which returns the following processor characteristics
- cache line size
- number and size of caches (L1, L2, L3)
- Number of Cores
- defines SMP or NUMA architecture
A) by “making software experiments”. It is recommended to read the article “Gallery of Processor Cache Effects” (at lecture # 2 we will examine examples from the article and outline ways to solve the problem)
B) by using JNA for operating system API calls

public class HardwareSpy { public int cacheLineSize() {...} public int cacheL1Size() {...} // -1  ,   L1 public int cacheL2Size() {...} // -1  ,   L2 public int cacheL3Size() {...} // -1  ,   L3 public int coreCount() {...} public int isSMP() {...} public int isNUMA() {...} } 

Contacts

Webinars, video recording, program source code and task verification are available only to those who register for the course.

I do Java online training (here are the programming courses ) and publish some of the training materials as part of the reworking of the Java Core course . You can see videos of lectures in the audience on the youtube channel , perhaps the video of the channel is better organized in this article .

skype: GolovachCourses
email: GolovachCourses@gmail.com