A short comparison of VHDL and Verilog to help beginners with FPGAs
Historically, it turned out that I started to study FPGA only at a new job.
These were the FPGA series from Altera .
Senior colleagues at the interruption recommended both AHDL and VHDL for programming these chips.
As a result, I settled on the VHDL language , since it is a high-level language, unlike ADHL .
Though the listing of the latter was much nicer.
And I began to study all the tricks and limitations of the VHDL language .
As a result, agreed on the idea that the language constructs are simply terrible, and the restrictions are redundant for the design of the equipment.
')
I will give an example of a listing from the article “Making a timer or first project on FPGA” .
I will not describe in detail how it works - just read the original article. I will try to express my impression of the listing as a whole.
For a start, an impossible block is the declaration of libraries. Moreover, libraries are necessary even for frequently used data types (std_logic) or type conversion function).
Make a beginner convert the internal variable of type integer to type std_logic_vector and set this value to an external port!
And what will we get? A few hours of painful search for how to do it.
As a result, it turns out that we need:
1. connect libraries:
2. writing integer to std_logic_vector port is not directly possible. You must use special type conversion functions! (Always resented the concept of type in projects for FPGA)
std_logic_vector (to_unsgined (,))
This record converts the low-order bits of the register to the std_logic_vector vector.
And at least 4 lines to write the number to the port.
Also for me the horror was the phenomenon of recording the vector:
vector (M downto N)
or
vector (M upto N)
the words downto and upto simply unbalanced me with their redundancy. In my opinion, they are redundant.
I am already silent about that. that numbers of different types are written differently:
integer is written as a normal number - 1, 2, 3, 4, 5
but with std_logic_vector there are problems.
The record has the form '1' and '0' for a single vector, but the vector of 2 or more digits by default CANNOT take decimal values. Only HEX or BIN .
Fortunately, my acquaintance with this language ended there and I plunged into the religion of the languages Verilog and SystemVerilog .
For me it was a revelation!
No extra entries. The listing is clean and straightforward. Each sign has a justified meaning and place.
Unfortunately, modern FPGA compilers do not fully support the standard of these languages, so not all their capabilities can be used. (In my personal practice, Quartus II poorly understood the project using procedures and functions.
He also poorly understood classes (or didn’t understand at all? I don’t remember).
Compare the listing itself in the SystemVerilog entry above:
As you can see, the number of rows has noticeably decreased. The listing itself is simpler and of the same type (numbers are written everywhere as numbers). The signal edge check unit migrated to the place where the process trigger was declared.
I also specifically expanded the functionality of the module to demonstrate the convenience and ease of data type conversion.
As you can see in the port description of the module, I entered the special eight-bit output port CNT_OUT . The data type of the port is logic .
Here it is worth making an easy digression about the types in SystemVerilog .
SV has two main types of data:
chains (wire)
registers (reg)
all other data types are not fully perceived by Quartus and therefore have not been used by me.
At the same time, the difference between these types (according to the standard) is that the type of chain cannot take on values.
The data type logic indicates that the compiler is free to decide for itself that it is a chain or register.
It is worth noting that Quartus ignores SV data types altogether during compilation. Its compiler allows you to use wire as a register and vice versa. Therefore, the use of the logic data type is somewhat arbitrary. We have a counter variable of the integer type (by default it is 32 bits) and an external output port of the type logic and a bit width of 8 bits.
Line CNT_OUT <= cnt; does the following:
each cycle to the CNT_OUT port is written to the lower 8 bits of the cnt register. (It should be noted that this record does not explicitly indicate the range of digits for writing to the port.
Therefore, 8 younger ones are taken).
Thus, we see that SV type conversion does not require specialized libraries and functions. All these tasks are solved by the compiler.
Also in SV there is a convenience in the form of automatic data bit leveling.
Those. if the project uses the integer data type, but according to the logic of operation it is clear that the value of this register does not exceed 255 (in the decimal system),
then after compilation this register will be 8 bit.
Thus, there is another liberty allowed by the SV standard - it does not require explicit alignment of register lengths.
In general, in my opinion the listing of SystemVerilog looks more harmonious and readable. What is achieved by the absence of long data type names and signal declaration lines and registers.
The recording of vectors is also easier and more accurate.
In general, these languages can be compared much deeper and longer. But I am sure that in most of the comparisons SV will show its beauty, compactness of the text and usability.
In general, SystemVerilog will appeal to programmers.
If you are an ingrained circuit designer, then you will like AHDL .
I do not cite it in comparison. it is a completely different topic and comparing it with the languages given in the article is the same as comparing assembler and S.
These were the FPGA series from Altera .
Senior colleagues at the interruption recommended both AHDL and VHDL for programming these chips.
As a result, I settled on the VHDL language , since it is a high-level language, unlike ADHL .
Though the listing of the latter was much nicer.
And I began to study all the tricks and limitations of the VHDL language .
As a result, agreed on the idea that the language constructs are simply terrible, and the restrictions are redundant for the design of the equipment.
')
I will give an example of a listing from the article “Making a timer or first project on FPGA” .
VHDL Source Code
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity Div_27Mhz_to_1Hz is port ( clk in std_logic; clk_out out std_logic ); end Div_27Mhz_to_1Hz; architecture div_behavior of Div_27Mhz_to_1Hz is Begin process(clk) variable cnt : integer range 0 to 27000000; begin if (clk'event and clk = '1') then if (cnt >= 13500000) then clk_out <= '1'; else clk_out <= '0'; end if; if (cnt = 27000000) then cnt := 0; else cnt := cnt + 1; end if; end if; end process; end div_behavior; I will not describe in detail how it works - just read the original article. I will try to express my impression of the listing as a whole.
For a start, an impossible block is the declaration of libraries. Moreover, libraries are necessary even for frequently used data types (std_logic) or type conversion function).
Make a beginner convert the internal variable of type integer to type std_logic_vector and set this value to an external port!
And what will we get? A few hours of painful search for how to do it.
As a result, it turns out that we need:
1. connect libraries:
use ieee.std_logic_1164.ALL; use ieee.std_logic_unsigned.all; use ieee.numeric_std.ALL;
2. writing integer to std_logic_vector port is not directly possible. You must use special type conversion functions! (Always resented the concept of type in projects for FPGA)
std_logic_vector (to_unsgined (,))
This record converts the low-order bits of the register to the std_logic_vector vector.
And at least 4 lines to write the number to the port.
Also for me the horror was the phenomenon of recording the vector:
vector (M downto N)
or
vector (M upto N)
the words downto and upto simply unbalanced me with their redundancy. In my opinion, they are redundant.
I am already silent about that. that numbers of different types are written differently:
integer is written as a normal number - 1, 2, 3, 4, 5
but with std_logic_vector there are problems.
The record has the form '1' and '0' for a single vector, but the vector of 2 or more digits by default CANNOT take decimal values. Only HEX or BIN .
Fortunately, my acquaintance with this language ended there and I plunged into the religion of the languages Verilog and SystemVerilog .
For me it was a revelation!
No extra entries. The listing is clean and straightforward. Each sign has a justified meaning and place.
Unfortunately, modern FPGA compilers do not fully support the standard of these languages, so not all their capabilities can be used. (In my personal practice, Quartus II poorly understood the project using procedures and functions.
He also poorly understood classes (or didn’t understand at all? I don’t remember).
Compare the listing itself in the SystemVerilog entry above:
Source code in SystemVerilog
module Div_27Mhz_to_1Hz ( input CLK, output logic CLK_OUT, output logic[7:0] CNT_OUT ); integer cnt = 0; always@(posedge CLK) begin if (cnt >= 13500000) begin CLK_OUT <= 1; end else begin CLK_OUT <= 0; end if (cnt == 27000000) begin cnt <= 0; end else begin cnt <= cnt + 1; end CNT_OUT <= cnt; end endmodule
As you can see, the number of rows has noticeably decreased. The listing itself is simpler and of the same type (numbers are written everywhere as numbers). The signal edge check unit migrated to the place where the process trigger was declared.
I also specifically expanded the functionality of the module to demonstrate the convenience and ease of data type conversion.
As you can see in the port description of the module, I entered the special eight-bit output port CNT_OUT . The data type of the port is logic .
Here it is worth making an easy digression about the types in SystemVerilog .
SV has two main types of data:
chains (wire)
registers (reg)
all other data types are not fully perceived by Quartus and therefore have not been used by me.
At the same time, the difference between these types (according to the standard) is that the type of chain cannot take on values.
The data type logic indicates that the compiler is free to decide for itself that it is a chain or register.
It is worth noting that Quartus ignores SV data types altogether during compilation. Its compiler allows you to use wire as a register and vice versa. Therefore, the use of the logic data type is somewhat arbitrary. We have a counter variable of the integer type (by default it is 32 bits) and an external output port of the type logic and a bit width of 8 bits.
Line CNT_OUT <= cnt; does the following:
each cycle to the CNT_OUT port is written to the lower 8 bits of the cnt register. (It should be noted that this record does not explicitly indicate the range of digits for writing to the port.
Therefore, 8 younger ones are taken).
Thus, we see that SV type conversion does not require specialized libraries and functions. All these tasks are solved by the compiler.
Also in SV there is a convenience in the form of automatic data bit leveling.
Those. if the project uses the integer data type, but according to the logic of operation it is clear that the value of this register does not exceed 255 (in the decimal system),
then after compilation this register will be 8 bit.
Thus, there is another liberty allowed by the SV standard - it does not require explicit alignment of register lengths.
In general, in my opinion the listing of SystemVerilog looks more harmonious and readable. What is achieved by the absence of long data type names and signal declaration lines and registers.
The recording of vectors is also easier and more accurate.
In general, these languages can be compared much deeper and longer. But I am sure that in most of the comparisons SV will show its beauty, compactness of the text and usability.
In general, SystemVerilog will appeal to programmers.
If you are an ingrained circuit designer, then you will like AHDL .
I do not cite it in comparison. it is a completely different topic and comparing it with the languages given in the article is the same as comparing assembler and S.
Source: https://habr.com/ru/post/191606/
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