New Brief: Samsung Launches First Vertical NAND Industry Vertical NAND Flash Memory with Vertical Layout
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Last week, Samsung Electronics announced the launch of a serial release of flash memory with 3D Vertical NAND (V-NAND) 3D volumetric layout, which is designed to make a breakthrough and provide opportunities to further reduce NAND Flash. The new 3D V-NAND flash memory will be used in a wide range of consumer electronics and corporate solutions, including embedded NAND and SSD drives.
For the past forty years, flash memory has been based on flat structures using floating gates. When the technology of the manufacturing process reached a class of 10 nm and less, further possibilities for reducing the scale of the chips were in question. The reason for this was the mutual influence of memory cells, which negatively affected the reliability of NAND flash memory, as well as the increased time and financial costs of chip production.
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The new Samsung V-NAND chips solve the above technical problems by achieving a new level of innovation in the chains, structure and production process. Samsung V-NAND provides 128 gigabit density in a single chip using the proprietary cell structure based on the new 3D Charge Trap Flash (CTF) architecture and vertical connection technology linking cells into a bulk array.
In order to achieve a new level of reliability of flash memory, Samsung has updated its CTF architecture, first developed in 2006. In the new NAND Flash architecture, the electric charge is temporarily placed in the “waiting cell” of a non-conducting flash memory layer, which consists of silicon nitride (SiN), instead of the traditionally used floating gates, which allowed to prevent interference during operation of neighboring cells.
The new V-NAND chips not only demonstrate increased reliability (twice, at least ten times the maximum), but also twice the write speed compared to conventional 10-nm flash memory based on floating gates .
In addition, one of the most important technological advances of the Samsung V-NAND memory is the fact that this vertical data exchange process allows more than 24 layers of cells to be formed in a single crystal, using a special etching technology that connects the layers electronically, punching holes from the highest to the lowest layer.
After nearly a decade of stubborn research in the field of NAND flash memory vertical layout, to date, Samsung has more than 300 patented technologies for 3D bulk memory around the world.
According to the research company IHS iSuppli, by the end of 2016 the global NAND flash memory market will reach a profit level of about $ 30.8 billion, which should be 11% of the average annual growth compared with the current year (about $ 23.6 billion).
Last week, Samsung Electronics announced the launch of a serial release of flash memory with 3D Vertical NAND (V-NAND) 3D volumetric layout, which is designed to make a breakthrough and provide opportunities to further reduce NAND Flash. The new 3D V-NAND flash memory will be used in a wide range of consumer electronics and corporate solutions, including embedded NAND and SSD drives.
For the past forty years, flash memory has been based on flat structures using floating gates. When the technology of the manufacturing process reached a class of 10 nm and less, further possibilities for reducing the scale of the chips were in question. The reason for this was the mutual influence of memory cells, which negatively affected the reliability of NAND flash memory, as well as the increased time and financial costs of chip production.
')
The new Samsung V-NAND chips solve the above technical problems by achieving a new level of innovation in the chains, structure and production process. Samsung V-NAND provides 128 gigabit density in a single chip using the proprietary cell structure based on the new 3D Charge Trap Flash (CTF) architecture and vertical connection technology linking cells into a bulk array.
In order to achieve a new level of reliability of flash memory, Samsung has updated its CTF architecture, first developed in 2006. In the new NAND Flash architecture, the electric charge is temporarily placed in the “waiting cell” of a non-conducting flash memory layer, which consists of silicon nitride (SiN), instead of the traditionally used floating gates, which allowed to prevent interference during operation of neighboring cells.
The new V-NAND chips not only demonstrate increased reliability (twice, at least ten times the maximum), but also twice the write speed compared to conventional 10-nm flash memory based on floating gates .
In addition, one of the most important technological advances of the Samsung V-NAND memory is the fact that this vertical data exchange process allows more than 24 layers of cells to be formed in a single crystal, using a special etching technology that connects the layers electronically, punching holes from the highest to the lowest layer.
After nearly a decade of stubborn research in the field of NAND flash memory vertical layout, to date, Samsung has more than 300 patented technologies for 3D bulk memory around the world.
According to the research company IHS iSuppli, by the end of 2016 the global NAND flash memory market will reach a profit level of about $ 30.8 billion, which should be 11% of the average annual growth compared with the current year (about $ 23.6 billion).
Source: https://habr.com/ru/post/190350/
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