Three-dimensional integration: what is it and why?

A little less than a year ago, Ivy Bridge processors appeared on the store shelves - the first microprocessors manufactured using 22nm technology, and, more importantly, the first using tri-gate transistors. Compared to their predecessors, these processors were significantly faster and consumed quite a bit of energy. But, ultimately, it was just another attempt to squeeze a little more from the materials and production technology, which had almost reached the limits of their capabilities.
Fortunately, there is another emerging technology that can extend the life of silicon electronics: three-dimensional integration. This is a technology that allows you to create systems with a high degree of integration, by stacking each other vertically and connecting different layers, in particular, semiconductor crystals. For example, you can take a DRAM memory crystal and place it on top of a microprocessor crystal. As a result, earlier parts that were several centimeters apart were now less than a millimeter apart. This reduces power consumption - the greater the distance, the more difficult the data transfer, and increases throughput.
The potential benefits of 3D integration include multi-functionality, increased performance, lower power consumption, miniaturization, cheaper and more reliable. Let's try to understand a little more about what this technology is.

A motivating example from real estate

Imagine that you and another 10,000 people live in a cozy cottage village of one-story houses. Compare this picture with the scenario where the same number of people inhabit the same high-rise building.
What territory will each of these settlements occupy? How long will it take you to make a friendly visit to a friend? How much will it cost to maintain the infrastructure of such a settlement (roads, electricity and water, etc.)? I am sure that this mental exercise will not cause difficulties, and I will not give answers, in view of their obviousness.

A bit of history

The modern level of integration technology development is already, in fact, its third generation.


Initially, it all began with attempts to merge two silicon crystals on a plane and pack them into a single case. This approach was used, for example, in the production of the Pentium Pro - in 1997, the production technology did not allow the integration of a large L2 cache into the chip of the processor core. Therefore, the L2 cache was made as a separate crystal and was in a common package with a processor chip.

Partially open Pentium Pro case. The cache crystal is on the right. You can see how regular his lithography is compared to the processor core.
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Surprisingly, after 15 years, this approach is very much alive, although it has somewhat changed. Referred to in the literature as “advanced packaging”, its modern implementation involves the use of a silicon transponser plate as a “mini-motherboard” connecting several crystals. The advantage of this approach is that the crystals can be positioned much closer than before, and no changes should be made to their design. It is expected that this approach will be used in new generations of multi-GPU video cards from Nvidia and AMD.

The next step in development is called 3d stacking. Although the layers of the components are located one on top of the other, the joints between the layers are located only at the edges. This approach, for example, has been successfully used by Apple for connecting DRAM and CPU in various gadgets for a long time.

3d stacking

Well, the last step - 3d TSV (through-silicon via), is characterized by the presence of end-to-end connections between the layers at an arbitrary point. At the moment, it is massively used only for connection with optical sensors in various digital photo / video equipment.

3d TSV

Factors affecting the development of 3d integration

The main factors influencing the development of this technology are presented in the following figure. Let us dwell on them in more detail.

Miniaturization and price reduction. If we recall the dimensions of microprocessors 10 years ago, it is obvious that if they were kept in size, they would not fit into the format of modern gadgets. The same phones, for example. It would seem that for more than forty years the execution of Moore's law gives a solution to this problem, effectively reducing the area with each generation of production technology. But you should not forget that the complexity of the devices and the number of transistors in them grows, exerting exactly the opposite effect. In addition, the cost of production grows about 2.5 times for each step from one process technology to another. How will 3d integration help here?

As for the size, the execution of the same number of transistors in several vertically arranged layers is more attractive from the point of view of linear dimensions. It's simple.

As for the price, we note that at least the total area of ​​silicon used in the device remains almost unchanged, but the size of each individual crystal decreases several times. This affects such an important parameter as the fraction of the yield of suitable crystals. Let me explain with an example: the crystal area of ​​the Itanium 2 processor is approximately 430 mm ² . Because of such an impressive size, only ~ 15% of the crystals produced on one silicon wafer ("wafer") (~ 10 pieces) are functioning. The larger the area, the greater the likelihood that it will encounter at least one manufacturing defect. And the cost of manufacturing one plate is about $ 6000. It is easy to calculate the cost of a single chip for a server microprocessor. For microprocessors that are not related to the server market, the release is advisable if the share of eligible people is at least 90%. That is not least due to a much smaller area. Thus, the use of 3d integration will significantly reduce the cost, especially for complex devices.

Intel Atom (Diamondville). Area 25mm ²

The next factor: the ratio of performance and power consumption . The increase in computing power leads to an increase in memory bandwidth requirements. What is especially important, for example, for video processing and other multimedia tasks. The closer the memory is physically located to the microprocessor, the less effort required to interact with it: less data transfer delay and less interference, which allows you to spend less energy on data transfer. It is difficult to imagine a memory chip located closer to the processor than lying on top of it.

An important argument in favor of 3D TSV, and not just 3d stacking, is: the width of the memory bus. These are usually dozens, or even hundreds of bits, and locating a bus of this capacity in areas specifically designed for I / O is not an easy task. Using TSV, however, gives dozens of times more density of conclusions and allows you to "save" both on the occupied area and on power consumption. And yet, you can, for example, increase the bus width and due to this, lower the frequency, remaining at the same level of performance.

The new standard of memory DRAM - Wide I / O, using TSV to connect to memory via a 512-bit bus, almost doubles the bandwidth compared to the standard LPDDR2 (Low-Power Double Data Rate 2), remaining at the same level of energy consumption.


Heterogeneous integration. If we are talking about the manufacture of a device on the surface of a silicon wafer, then the question arises about the choice of technological parameters. Within the framework of the same technology, it is possible to make a choice between, for example, the transistor speed and the leakage current. In addition, if we are talking about something more small-scale than microprocessors, the question of choosing a technology is also not easy. Using the latest process technology entails the need to redo the design at the physical level for the previously used IP blocks. This worsens the indicator such as IP reuse, incurs monetary and, more importantly, time costs.

Using 3d integration allows you to combine into one device parts made with different technological parameters, or even using different technological processes. This allows in many cases to gain an advantage. For comparison, I will give a table showing the optimal characteristics for the actual memory cells and the associated logic. As you can see, there are many differences.


That's all for now. In the next part, I will try to talk about the problems associated with 3d integration (and there are many advantages, and where is their realization?) And finish the story.