Briefly about the new: Samsung is ready to produce 14-nm FinFET chips
Samsung Electronics announced that it has reached a new milestone in the development of 14-nanometer tech. process for FinFET semiconductors by successfully launching the “tape out” design of several test chips. “Tape out” is a digital data package (base), on the basis of which a photo mask is made at the factory for the subsequent lithographic production of chips. Previously, similar projects were transferred to the plant in the form of paper printouts, but then were replaced with reels with magnetic tape (tape). Of course, in the Internet era, no one uses such old-school means for transmitting information, but the term has taken root. In reality, this means that the project team has completed its part of the work, and now it’s up to the commissioning of production.
As part of the development of 14-nm “vertical” FinFET transistors, Samsung, together with ecosystem partners: ARM and software developers Cadence, Mentor and Synopsys, prepared several test chips for release, including ARM Cortex-A7 compute cores ARM architecture elements big.little); ultra-low-power chip and logic elements based on SRAM base and many analog blocks.
The Cortex-A7 test chip was developed by Cadence in collaboration with ARM and Samsung. The company Cadence has provided a complete description of the synchronous digital circuit (RTL), based on a set of tools that require dual formation of structures, which has been thoroughly tested on the 20-nm tech. process. ARM, in turn, used Cadence tools to develop the 14-nm FinFET library. Also, these tools were used to compile a complete description of the synchronous digital circuit of the processor core based on 14-nm tech. Samsung's FinFET process and chip-based integration and verification.
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In addition, Samsung is also expanding the scope of cooperation with Mentor Graphics to launch a complete solution based on 14-nanometer FinFET, which will save future customers from problems in the design development process, testing, joint optimization and post-design at the production stage. Together, the companies plan to solve the main problems associated with the difficulties of multilayer three-dimensional lithography, features of FinFET transistors and more complex requirements for the reliability of these solutions.
The set of tools needed for the development of new chips (PDK) is available today: customers can begin designing on the basis of test models, project standards guidelines and technology guidelines that have already been drawn up and tested in Samsung's R & D laboratories. This PDK includes design flows, routers, and other features to support new device structures, local connections, and advanced routing rules. By providing its customers with quick access to all the design elements of the infrastructure of new chips, Samsung, thus, invests in the development and early implementation of the entire FinFET ecosystem.
As part of the development of 14-nm “vertical” FinFET transistors, Samsung, together with ecosystem partners: ARM and software developers Cadence, Mentor and Synopsys, prepared several test chips for release, including ARM Cortex-A7 compute cores ARM architecture elements big.little); ultra-low-power chip and logic elements based on SRAM base and many analog blocks.
The Cortex-A7 test chip was developed by Cadence in collaboration with ARM and Samsung. The company Cadence has provided a complete description of the synchronous digital circuit (RTL), based on a set of tools that require dual formation of structures, which has been thoroughly tested on the 20-nm tech. process. ARM, in turn, used Cadence tools to develop the 14-nm FinFET library. Also, these tools were used to compile a complete description of the synchronous digital circuit of the processor core based on 14-nm tech. Samsung's FinFET process and chip-based integration and verification.
')
In addition, Samsung is also expanding the scope of cooperation with Mentor Graphics to launch a complete solution based on 14-nanometer FinFET, which will save future customers from problems in the design development process, testing, joint optimization and post-design at the production stage. Together, the companies plan to solve the main problems associated with the difficulties of multilayer three-dimensional lithography, features of FinFET transistors and more complex requirements for the reliability of these solutions.
The set of tools needed for the development of new chips (PDK) is available today: customers can begin designing on the basis of test models, project standards guidelines and technology guidelines that have already been drawn up and tested in Samsung's R & D laboratories. This PDK includes design flows, routers, and other features to support new device structures, local connections, and advanced routing rules. By providing its customers with quick access to all the design elements of the infrastructure of new chips, Samsung, thus, invests in the development and early implementation of the entire FinFET ecosystem.
Source: https://habr.com/ru/post/163731/
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