IBM opens the way for flexible electronics

Good evening, dear users!

The moment when we will roll a flexible smartphone into a tube, has become even closer. For details - we ask under cat.







At the International Electron Devices Meeting, held in San Francisco, IBM introduced a new and relatively inexpensive technology for making silicon electronics on a flexible plastic substrate.



On the one hand, IBM points to a slight decrease in the performance of transistors in the manufacturing process, but on the other hand, studies show that a flexible and affordable technique can still be created with normal processes at room temperature.

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According to Davood Sharjerdi, an employee of IBM's TJ Watson Research Center, during testing of other one- and two-dimensional materials in flexible electronics, problems such as high contact resistance and unreliable gate insulation occurred. In addition, other methods require either non-standard processes and materials, or need high temperatures during the production process.



The IBM approach, based on controlled chipping or flaking, was described earlier this year as a kerfless technique for removing silicon, germanium and III-V layers, which was used by IBM as proof of the possibility of making low-power photovoltaic cells .



This approach is, oddly enough, simple. The chip substrate is cleaved and transferred to a flexible plastic tape. The result is a device with a gate length of less than 30 nm and a gate spacing of 100 nm.



According to specialists from IBM, they managed to achieve the best performance for flexible SRAM memory circuits with a voltage of VDD = 0.6V and a ring oscillator with a delay period of 16 ps at 0.9V power.



The process is as follows: it all starts with a substrate (a very thin SOI-ETSOI), onto which a stress layer of nickel with a thickness of about 5–6 microns is allocated. (The ICs are manufactured using 22 nm CMOS technology using ETSOI plates with a diameter of 300 mm). A layer of elastic polyimide tape is applied over the stress layer. Then, at room temperature from one edge of the substrate, scientists provoke a "stress-gap" and spread a "mechanically controlled" fracture front over the entire surface of the substrate.



IBM uses ETSOI technology for two reasons. The first is the ultrathin substrate thickness (60 angstroms), which allows scaling the process below 30 nm and achieving a high density of circuit elements. The second is the presence of unalloyed transistor channels reduces the uneven distribution of impurities, which allows for a significant variation in the voltage values ​​on the chip.



In order to improve the mechanical flexibility, the researchers removed the excess silicon under the buried oxide layer.







The second step to increase flexibility was to transfer the circuit onto a plastic substrate, after which the “relatively thick” polyimide tape and nickel layer were removed. Polyimide is easy to break down because it is bonded to the substrate with a thermally removable adhesive; Nickel is removed by chemical etching.



IBM reported a slight decrease in the speed of the circuits on the flexible samples compared to the characteristics before transfer to the flexible ribbon, and the p-type transistors have a greater deterioration of the parameters than the n-type (by 30–40%).



To determine the causes of deterioration, IBM monitored the spallation on another ETSOI plate using the same processing steps. This time the sample was rigidly fixed on a silicon wafer instead of being transferred to a flexible plastic substrate. As a result, IBM scientists came to the conclusion that the reduction in the characteristics of p-type transistors was most likely caused by the mechanical action of the probe, and not by the stresses caused by the cleaving process.



According to Davud Sharyerdi, in the laboratory, the yield of samples was 97%, and the problems they encountered were caused by a nickel deposition tool that affected this layer. He also added that the process is reproducible, and knowing the location of the stressor in the nickel layer, it is possible to determine the depth of spallation with an accuracy of plus or minus 1 micron.



Via eetimes