The future of the process, or when the law of Moore "die"?

Due to the fact that Moore's law has been fulfilled for over 50 years and the topic of how much he “still remains” is discussed everywhere, including on Habré, I would like to share the thoughts and plans of those who will have to approve and support this law at least in the coming years.

Below is my humble translation of the blog of people responsible for architecture and production at Intel: Mark Bohr and Sanjay Natarajan about how long, from their point of view, the technical process will be reduced and what technology, from their point of view, will help support progress in this direction.

')
Recently, the question has often arisen: “Is the process of reducing the size of transistors coming to an end?” Since no one believes that the process of improving technology can stop altogether, the option of this question would be more reasonable: “Does the development and implementation of new technical processes become technically or practically impossible?” about every two years, as predicted by Moore’s law almost 50 years ago? ”
Before answering this question, first look at the story. At one time, the development of semiconductor manufacturing technology was much easier. The basic architecture of MOSFETs was fixed, and the path to developing a new process was clear and simple: to reduce the size, reduce the vertical size, reduce the electric field and — voila — the new faster and more energy-efficient transistor is ready. Of course, inventions such as pinpoint and halo (halo) implantations, silicide oxides and nitride shutters were necessary to solve problems along the way, but the basic architecture remained the same for many generations. (When we talk about inventions, let's not forget about reducing the length of interconnects, where copper conductors and planarization are proposed.)

End scaling?

Even during the heyday of these technologies, industry experts predicted the end of scaling. Experts say, “Optical lithography will reach its limits in the range of 0.75-0.50 microns,” “Minimal geometries [of transistors] will be reached in the range of 0.3 to 0.5 microns,” “X-ray lithography will be needed for sizes less than 1 micron,” “Copper interconnects will never work,” and “Scaling will end in about 10 years,” were done publicly, and everyone seems strange after a while.
Perhaps the 130-nm technology was the latest true technology in this architecture. The beginning of the 1990s marked a huge change in this industry in connection with the invention of Intel uniaxial silicon stressed in 90-nm technology. This change is marked by the use of silicon-germanium alloys in the source / drain of the PMOS (p-channel MOS) transistor, it opened an era of major changes in materials in addition to the existing geometric and electrical scaling. The 65nm stage was the last opportunity to use the industry's workhorse, the SiON gate dielectric. Starting at 45nm, Intel made the transition to an exotic dielectric based on hafnium dioxide with a high dielectric constant k and a complex sandwich structure of films. Finally, the 22-nm stage marked the end of the 50th year of life of the planar MOS transistor and the transition to the tri-gate technology of 3D transistors. The current state of the technology resembles the transistor of the late 1980s, about as much as Ferrari resembles a horse-drawn carriage.



Not only the structure of the transistor and materials has changed dramatically over the past decades, but the goal of scaling the transistor has also changed. In the 1980s and 1990s, classical scaling provided significant improvements in the transistor speed for microprocessor operation at higher operating frequencies. But we paid the price for a very high power density with its ever higher leaks. The 2000s opened an era when the power density limit and the market demand for mobile computers changed the focus of transistor technologies from increased performance to reduced power consumption. Modern computers, whether they are high-performance servers or low-powered mobile phones, all require energy efficiency and reduced energy leakage. And the growing interest in systems-on-a-chip (SOC) is giving increasing importance to creating a wide range of devices on a single chip, from high-performance transistors with ultra-low leakage.

Radical new approaches

The historical perspective is very important because it reminds us that the only constant in our industry is change (or, as Yogi Berra put it, “the future is not what it was”). In the future, a radically new architecture can create another colossal shift when gradual improvement stops working. There are many potentially attractive options for technologies like tunnel field-effect transistors, BISFET (bilayer pseudospintronic field-effect transistors) transistors, graphene-based field-effect transistors, and spin-based field-effect transistors. All of them are actively investigated in leading semiconductor companies.

Another trend that is becoming increasingly important is the closer integration of technological processes, product design and architecture. Over the past several generations, constraints in the scaling process have led to design constraints, which, in turn, require closer joint optimization between design and process to achieve a better result. This trend is likely to continue and even grow. The future will include the integration of new processes, design and architecture, such as 3D packaging inside the chip, not just inside TSV (through-silicon via) packaging and new approaches to computing, such as a process optimized for non-Boolean logic.

It is possible that tomorrow the new process technology architecture will make such a strong breakthrough that the “today's Ferrari” will look like an ancient “horse-drawn carriage”. Since we live and work in this amazing time for the semiconductor industry, and we hope to see another 50 years of "work" Moore's law.