Once again about WOL

It is necessary to turn on the computer over the network. Wake-on-LAN is not working.
The proposed method is universal, but non-standard and implies the existence of creative optimism "by all means".

I once had an FTP server. In fact, it was the usual comp sample of 2004. Here in p.7 I wrote that there is such a WOL and subtlety in configuring the router's ARP table, so that it would not forget which port it has on this computer (after the computer’s power is turned off). And it just so happened that I didn’t have any problems with the whole thing - the corresponding option was turned on in the BIOS and the server was energetically turned on at any time of the day or night regardless of whether the power was turned off or not.
But everything good always has a tendency to end: either you get used to it, or it disappears. The computer was taken away from me ...
However, recently there was a need for your FTP again. And since in the future I still want to hang something on him, I decided to assemble a new relatively productive computer for these purposes. And here, the ASUS P8H77-M + Intel® Core ™ i3-2105 + 2 x 4Gb Corsair Vengeance CMZ4GX3M1A1600C9B platform in the Thermaltake VK72721N2E SD200 package appeared in my home. After the wild enthusiasm of households, the computer was tucked under the TV instead of the dismissed VHS + DVD combine harvester, which has been there since 2004, for a stylish look of the body. As an experiment, I decided to complicate my life and put the Windows on this server, and in Windows I got VMWare with my three virtual computers. One of the virtual computers and has become a new FTP-server. After port forwarding on the router and in the VMWare virtual network environment, the FTP server began to respond and work properly.


Then I, of course, remembered WOL, corrected port forwarding on the router, downloaded the “Wake On LAN” program for android (I used to use the wakeonlan.ru service). Remember all good things? And so, one day I was unable to remotely turn on this computer. I couldn’t take 130GB with me anyway and was therefore extremely saddened. Bad words went to the designers of the implementation of WOL in general and the engineers of ASUS in particular. I apologize if someone hiccupped that day, but I was really sad. After debriefing, it turned out that this motherboard should be included at least once, which would then wake up at the WOL. And if I am not at home, and the electricity was turned off (the light was promised to be turned off by the end of December 2012)? That is, I can not remotely turn on the computer. The BIOS has a power recovery function, i.e. if the computer was turned on when a power failure occurred, then after the power appears, the computer will start itself. And if it was off? Yes, in the foreseeable future, another virtual machine will be under the torrent and the computer will work around the clock, but all this is some form of disorder.
I was interested in this question on the Internet and in knowledgeable people. Knowledgeable people usually work with more serious network equipment and they cannot really say how to turn out in this situation. Little of! Many have told me that this is normal, i.e. the computer needs to know which device to power on to wait for the command to turn on. And quite a lot of people assured me that the computer will wake up normally only if it is turned on via the Start (???). What was said on the Internet I will not retell, but sometimes I frankly had fun.

There was a question: what to do?
There were a lot of ideas. From the idea of ​​the advancing sidiroma of some “normal-awakening” ancient computer to the idea of ​​outputting the WOL signal of a network chip through some kind of logic to the connector of the computer's power button. The problem of working at the element base level is that there is no oscilloscope at home (C1-112A is not considered). But then I suppressed my appetites and decided to make a decision independent of computer hardware. A network card D-Link DGE-528T was found in the bins. It houses a wonderful white connector WOL. If you look pinout, the connector contains three signals: + 5VSB, GND, Ring. Many old motherboards also had the same connector, now they are leaving this trend. Obviously, the power to the network card is supplied autonomously. The computer itself was turned on either when the power button was pressed or after the Ring signal was received. There is no such connector on ASUS P8H77-M!
And here, by the way, the released motherboard rover board with the FPGA was onboard. I decided to make a lifelong universal solution for any computer (this one can also be selected):
1) insert any network card with a WOL connector on board into the computer;
2) in the comp somewhere we fasten the board with the FPGA;
3) connect the interface board for WOL to the FPGA board;
4) we connect the WOL connectors on the network card and interface board with the manufactured special cables, connect the power button and PWR_BUT connector of the motherboard to the interface board, and also supply + 5VSB power to this board.
Thus outline the range of tasks:
1) for the FPGA, a firmware is needed that would interrogate the signals from the power button on the computer and the Ring signal from the network card and, if detected, would output a signal to the PWR_BUT connector of the motherboard;
2) the interface board should power the board with the FPGA (set the stabilizer at + 3.3V), and it would also be nice to have a decoupling for WOL and PWR_BUT just in case (set a couple of optocouplers);
3) you need to make cables: 3-wire for WOL (the connector on the FPGA side in 2.54 pitch, and on the network card side 2mm), 2-wire for connecting PWR_BUT (2 connectors in 2.54 pitch), 2 wire for power (1 connector with Step 2.54, and attach the other end somehow to the power connector of the motherboard - to the wires GND and + 5VSB).
')
Rolled up the rukov.
I wrote the firmware for half an hour. The firmware is trivial: poll two ports and output, for example, a half-second pulse to the third port. I took into account the bounce of the power button, detected only the front of the Ring signal, made an accurate time generator with ranges up to 24 hours and other trifles - I had fun as I could) The firmware was much harder than the first option, but still half of the FPGA remained free. A universal place was consumed by a universal time generator, which was connected to the project as a module.
I also made the cables in half an hour. But I had everything at hand - lucky with connectors.
With the interface card, I suffered the whole of the following evening. I cut the board myself from a piece of double-sided prototype printed circuit board. The board is worn on the Mars Rover board by a “bridge” on the “Rigth Motor” and “Left Motor” connectors. “Rigth Motor” was given over to WOL, and I forwarded the second connector to the interface board - paradoxically, but the absence of a woman in her personal life contributes to an equally interesting pastime and it is not known what else she wants to be screwed to this board. Since I was too lazy to solder the wiring, and I have a lot of solder, I simply “grew” the necessary tracks. It turned out inconspicuously and, in principle, I do not advise doing this. A DC-DC stabilizer was also found at home, but there were no optocouplers. Instead, he packed the pads and for the week everything was abandoned. Two weeks later I put the optocouplers and decided to check how it all will work.




The hardest part was cutting the ATX power connector. On the Internet, there are a lot of tips on how to push a clip from a stapler (well, I don’t have an extractor) into the slot to bend the clips. I even watched a video on some site. But I didn’t want a contact to get out of the connector. Calling for the help of well-known words, I spent almost two hours breaking a needle and re-selling a few clips. But it turned out to be civilized)


The solution is operational and allows you to enable / disable the computer from the power button on the case and turn the computer on over the network by issuing a WOL command. Unfortunately, the computer cannot be switched on over the network - after the power is turned on, the network card stops issuing the Ring signal. In addition, there is a reserve for further creativity! For example, you can remake the FPGA firmware so that after receiving eight eight WOL commands within 20 seconds, the USB controller will be powered. An inserted USB flash drive in a USB controller would be mounted by a machine into a virtual machine and, using FTP, under a special login and special password, a daddy would be available, containing, for example, a document with a password on the keyboard)

It remains to carefully secure the device in the system unit and put it on duty. What will be done when the ordered fee arrives. And the current one will come back to control the car alarm system - when you are bathing it is convenient to lock all things in the car and set the timer to open after a set time)))

Price issue:
- network card D-Link DGE-528T = 300r.
- fee Mars Rover + programmer to it (if needed) + delivery by mail Russia = 1000r. + 600r. + 150r.

Below is the text of the firmware for the FPGA and, schematically, the interface board. For newcomers to VHDL, I think the text will be useful. It is easy to write the time generator - they counted it up to CLOCK - that’s your second. When pripovke do not forget for the ports F0 and F1 to install "Schmitt Trigger Input" and turn on the pull-up resistor. On the interface board with resistors, these inputs are also pulled up, but for other purposes - static protection.

---------------------------------------------------------------------------------------------------------- -- Company: House -- Engineer: AlexanderS -- -- Create Date: 13/06/2012 -- Modification Date: --/--/---- -- Module Name: manag_pc -- Project Name: - -- Version: v.1.1 -- Description:     PWR ,  WOL    --    /  PWR SW    ---------------------------------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; --use IEEE.STD_LOGIC_SIGNED.ALL; use IEEE.NUMERIC_STD.ALL; --use IEEE.MATH_REAL.ALL; --library UNISIM; --use UNISIM.VComponents.ALL; entity project is GENERIC ( ----------   ---------- CLOCK : integer := 100000000 --   , [;  1000] ); Port ( ----------  ---------- led: out std_logic_vector(7 downto 0) :=(others=>'0'); f0: in std_logic_vector(9 downto 0) :=(others=>'1'); f1: in std_logic_vector(9 downto 0) :=(others=>'1'); f2: out std_logic_vector(9 downto 0) :=(others=>'0'); ----------    ---------- CLK: in std_logic :='0' --    ( CLOCK) ); end project; architecture Behavioral of project is signal df : std_logic_vector(5 downto 0) :=(others=>'0'); signal sw_lock : std_logic :='0'; signal hl : std_logic_vector(7 downto 0) :=(others=>'0'); signal PWR_BUT1, WOL1, PWRB_on, WOL, lock : std_logic :='0'; signal PWR_BUT2, WOL2 : std_logic :='1'; signal st : integer range 3 downto 0 :=0; signal sec0125, sec025, sec05, sec, sec2, min, hour, day, res_time : std_logic :='0'; signal time_s, time_m : std_logic_vector(5 downto 0) :=(others=>'0'); signal time_h : std_logic_vector(4 downto 0) :=(others=>'0'); COMPONENT gen_time is --   GENERIC ( CLOCK : integer := 100000000 ); Port ( ----------  ---------- sec0125: out std_logic :='0'; sec025: out std_logic :='0'; sec05: out std_logic :='0'; sec2: out std_logic :='0'; sec: out std_logic :='0'; time_s : out std_logic_vector(5 downto 0) :=(others=>'0'); min: out std_logic :='0'; time_m : out std_logic_vector(5 downto 0) :=(others=>'0'); hour: out std_logic :='0'; time_h : out std_logic_vector(4 downto 0) :=(others=>'0'); day: out std_logic :='0'; ----------    ---------- RES: in std_logic :='0'; CLK: in std_logic :='0' ); end COMPONENT; begin Inst_gen_time: gen_time --   GENERIC MAP( CLOCK => 100000000 ) Port MAP ( sec0125 => sec0125, sec025 => sec025, sec05 => sec05, sec => sec, sec2 => sec2, time_s => time_s, min => min, time_m => time_m, hour => hour, time_h => time_h, day => day, RES => res_time, CLK => CLK ); res_time <= '0'; ---- BEGIN  - Process(CLK) begin if (CLK'Event) and (CLK='1') then if (sw_lock = '0') then if (f0(0) = '0') or (f1(0) = '0') then sw_lock <= '1'; end if; df(0) <= not f0(0); hl(6) <= f0(0); df(1) <= not f1(0); hl(7) <= f1(0); elsif (sec0125 = '1') then sw_lock <= '0'; end if; end if; if (df(2) = '1') then f2 <= (others=>'1'); else f2 <= (others=>'0'); end if; led <= hl; end if; end process; ----- END  - --- BEGIN process(CLK) begin if (CLK'event and CLK = '1') then PWR_BUT1 <= df(0); PWR_BUT2 <= not PWR_BUT1; WOL1 <= df(1); WOL2 <= not WOL1; if ((PWR_BUT1 = '1') and (PWR_BUT2 = '1')) then --      PWRB_on <= '1'; elsif ((PWR_BUT1 = '0') and (PWR_BUT2 = '0')) then --      PWRB_on <= '0'; elsif ((WOL1 = '1') and (WOL2 = '1')) then WOL <= '1'; else WOL <= '0'; end if; --    WOL if (PWRB_on = '1') and (lock = '0') then --    df(2) <= '1'; hl(0) <= not hl(0); lock <= '1'; elsif (PWRB_on = '0') and (lock = '1') then --    df(2) <= '0'; lock <= '0'; else --   WOL case st is when 0 => if (WOL = '1') then st <= st + 1; end if; --      when 1 => df(2) <= '1'; if (sec025 = '1') then st <= st + 1; end if; when 2 => if (sec025 = '1') then st <= st + 1; end if; when 3 => hl(0) <= not hl(0); df(2) <= '0'; st <= 0; when others => null; end case; end if; end if; end process; --- END end Behavioral; 

It is still possible to fasten the UPS control to the FPGA board. And this duty computer with its network launch will still unlock the possibility of network switching on other equipment)))

PS
One friend said that without the support of equipment manufacturers, it would be very difficult to do all this (WOL) and there is no point in taking, etc. etc. Argued with him to "just like that" ...
Well, who said that we can not something? :)