We program SSRAM on FPGA
Finally, I also decided to throw in my 5 kopecks into the development of such an interesting, but narrowly presented topic here - programming FPGAs and peripherals. In particular, in this article I will briefly describe the work of a fairly simple, but such an important type of memory as SSRAM and demonstrate my simple example of its control performed with Quartus II using the Verilog HDL language.
SSRAM is a synchronous static random access memory. In general terms, this means that you can access data located in an arbitrary memory cell, the memory is volatile (turning off the power will lead to the loss of all data), all operations are performed on a positive clock signal differential.
This type of memory is very fast, access to any cell occurs at the same speed, is simply organized and is much easier to describe than DRAM. But, of course, it also has disadvantages: the complexity of the cell device (6 elements, while in DRAM - 2), as a result of this - a small recording density, high power consumption and high price.
If we talk about the use of SSRAM - then the best example is the processor cache.
I use the Terasic DE2-70 debug board, which is based on Cyclone II crystal. You may use any other plis by simply changing the pins in the project.
The figure below shows the image of the board, the location of its main elements.
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We have 2 MB of memory, organized as 512K x 36 bits.
A general description of this memory chip can be found in the data sheet at the end of the article, as well as a detailed description of the operation. I will not stop there.
For a better understanding, you should start with a description of the finished device.
Management bodies:
1. 1 group of switches. Responsible for setting the address. 4 bits i. we have 16 addresses.
These are the low order bits of the address bus, the rest do not change and are set to “0”.
2. 2 group switches. Responsible for setting the recorded value. Again, 4 bits - 16 different values. 1 low-order bit of each 8-bit data bus is used, the rest are ignored when reading. This is done for more indicative of the system, and for a simpler transition to work with large values in the future.
3. Record button. When pressed, the set value is written to the memory at the specified address.
4. LCD on / off switch.
5. Push button to refresh the display. Just in case.
The display is divided into 3 areas: the address, the value located at this address, and the recorded value.
Our memory chip has a two-way data bus, i.e. it uses the same bus for both writing and reading. It is made as follows. The control signal wr2 is formed in the controller and is responsible for switching the directivity of the bus.
Now consider the controller itself
Clock input signal is connected to a quartz oscillator installed on the board - 50 MHz. The output signal out is transmitted to the display.
The output signals from A to GW_n are transmitted directly to the memory chip.
I will not go into the description of the work of the code, it is quite simple and those who wish can familiarize themselves with it by taking the source code at the end of the article. Instead, consider the behavior of signals in time.
When the button is pressed, the wr signal is switched to “0”. After this, we see a sequential change in the states of the control signals: the command for capturing an address into the register of the chip, writing data into memory at this address, again the command for capturing an address, and finally, the command for reading at this address. After that, the controller remains in the last state. After that, when the address changes, it is captured into the memory register and read. Along with these, the controller generates a signal wr2, which is equal to “0” at the time of the write command and sets the direction of the double-sided data bus of the memory to write.
The write and read commands are single, i.e. after the address capture command, the internal controller of the memory chip will accept only the first reading command, the rest will simply be ignored. In view of this, it is permissible to use the read command as a passive state of the controller.
Recordable and readable data, as well as the address is continuously transmitted to the controller of the LCD display. But this is a topic for a separate article.
It should be noted that the above scheme, only the simplest example. This chip also supports the packet write / read mode, the ability to write one or several 8-bit buses, without affecting the others already stored in the memory, has different possibilities for the implementation of commands.
Of course, this is a simple, flawed project by a novice developer, through which I got acquainted with the basics of working with memory. But, I hope, it will arouse the interest of the public, and maybe it will give someone an impetus to start exploring this area.
rghost.ru/20959811 - debug board datasheet
rghost.ru/20960231 - datasheet memory chips
rghost.ru/20960351 - project
What is SSRAM
SSRAM is a synchronous static random access memory. In general terms, this means that you can access data located in an arbitrary memory cell, the memory is volatile (turning off the power will lead to the loss of all data), all operations are performed on a positive clock signal differential.
This type of memory is very fast, access to any cell occurs at the same speed, is simply organized and is much easier to describe than DRAM. But, of course, it also has disadvantages: the complexity of the cell device (6 elements, while in DRAM - 2), as a result of this - a small recording density, high power consumption and high price.
If we talk about the use of SSRAM - then the best example is the processor cache.
Instead of intro
I use the Terasic DE2-70 debug board, which is based on Cyclone II crystal. You may use any other plis by simply changing the pins in the project.
The figure below shows the image of the board, the location of its main elements.
')
We have 2 MB of memory, organized as 512K x 36 bits.
A general description of this memory chip can be found in the data sheet at the end of the article, as well as a detailed description of the operation. I will not stop there.
From words to deeds
For a better understanding, you should start with a description of the finished device.
Management bodies:
1. 1 group of switches. Responsible for setting the address. 4 bits i. we have 16 addresses.
These are the low order bits of the address bus, the rest do not change and are set to “0”.
2. 2 group switches. Responsible for setting the recorded value. Again, 4 bits - 16 different values. 1 low-order bit of each 8-bit data bus is used, the rest are ignored when reading. This is done for more indicative of the system, and for a simpler transition to work with large values in the future.
3. Record button. When pressed, the set value is written to the memory at the specified address.
4. LCD on / off switch.
5. Push button to refresh the display. Just in case.
The display is divided into 3 areas: the address, the value located at this address, and the recorded value.
Our memory chip has a two-way data bus, i.e. it uses the same bus for both writing and reading. It is made as follows. The control signal wr2 is formed in the controller and is responsible for switching the directivity of the bus.
Now consider the controller itself
Clock input signal is connected to a quartz oscillator installed on the board - 50 MHz. The output signal out is transmitted to the display.
The output signals from A to GW_n are transmitted directly to the memory chip.
I will not go into the description of the work of the code, it is quite simple and those who wish can familiarize themselves with it by taking the source code at the end of the article. Instead, consider the behavior of signals in time.
When the button is pressed, the wr signal is switched to “0”. After this, we see a sequential change in the states of the control signals: the command for capturing an address into the register of the chip, writing data into memory at this address, again the command for capturing an address, and finally, the command for reading at this address. After that, the controller remains in the last state. After that, when the address changes, it is captured into the memory register and read. Along with these, the controller generates a signal wr2, which is equal to “0” at the time of the write command and sets the direction of the double-sided data bus of the memory to write.
The write and read commands are single, i.e. after the address capture command, the internal controller of the memory chip will accept only the first reading command, the rest will simply be ignored. In view of this, it is permissible to use the read command as a passive state of the controller.
Recordable and readable data, as well as the address is continuously transmitted to the controller of the LCD display. But this is a topic for a separate article.
In conclusion
It should be noted that the above scheme, only the simplest example. This chip also supports the packet write / read mode, the ability to write one or several 8-bit buses, without affecting the others already stored in the memory, has different possibilities for the implementation of commands.
Of course, this is a simple, flawed project by a novice developer, through which I got acquainted with the basics of working with memory. But, I hope, it will arouse the interest of the public, and maybe it will give someone an impetus to start exploring this area.
rghost.ru/20959811 - debug board datasheet
rghost.ru/20960231 - datasheet memory chips
rghost.ru/20960351 - project
Source: https://habr.com/ru/post/128345/
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